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Searched refs:halfword (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/arch/mips/kernel/
H A Dbranch.c265 u16 halfword; in __microMIPS_compute_return_epc() local
274 __get_user(halfword, pc16); in __microMIPS_compute_return_epc()
277 word = ((unsigned int)halfword << 16); in __microMIPS_compute_return_epc()
280 if (!mm_insn_16bit(halfword)) { in __microMIPS_compute_return_epc()
281 __get_user(halfword, pc16); in __microMIPS_compute_return_epc()
285 word |= halfword; in __microMIPS_compute_return_epc()
289 if (get_user(halfword, pc16)) in __microMIPS_compute_return_epc()
292 word = ((unsigned int)halfword << 16); in __microMIPS_compute_return_epc()
294 if (!mm_insn_16bit(halfword)) { in __microMIPS_compute_return_epc()
296 if (get_user(halfword, pc16)) in __microMIPS_compute_return_epc()
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H A Djump_label.c81 insn_p->halfword[0] = insn.word >> 16; in arch_jump_label_transform()
82 insn_p->halfword[1] = insn.word; in arch_jump_label_transform()
H A Dunaligned.c623 u16 halfword; in emulate_load_store_microMIPS() local
639 __get_user(halfword, pc16); in emulate_load_store_microMIPS()
642 word = ((unsigned int)halfword << 16); in emulate_load_store_microMIPS()
645 if (!mm_insn_16bit(halfword)) { in emulate_load_store_microMIPS()
646 __get_user(halfword, pc16); in emulate_load_store_microMIPS()
650 word |= halfword; in emulate_load_store_microMIPS()
654 if (get_user(halfword, pc16)) in emulate_load_store_microMIPS()
657 word = ((unsigned int)halfword << 16); in emulate_load_store_microMIPS()
659 if (!mm_insn_16bit(halfword)) { in emulate_load_store_microMIPS()
661 if (get_user(halfword, pc16)) in emulate_load_store_microMIPS()
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H A Dprocess.c424 if (is_mmips && mm_insn_16bit(ip->halfword[0])) { in get_frame_info()
425 insn.word = ip->halfword[0] << 16; in get_frame_info()
428 insn.word = ip->halfword[0] << 16 | ip->halfword[1]; in get_frame_info()
/openbmc/qemu/target/s390x/tcg/
H A Dvec.h20 uint16_t halfword[8]; member
60 return v->halfword[H2(enr)]; in s390_vec_read_element16()
103 v->halfword[H2(enr)] = data; in s390_vec_write_element16()
/openbmc/linux/arch/mips/math-emu/
H A Ddsemul.c258 .halfword = { ir >> 16, ir } in mips_dsemul()
261 .halfword = { break_math >> 16, break_math } in mips_dsemul()
/openbmc/qemu/tests/tcg/tricore/c/
H A Dcrt0-tc2x.S239 st.h [%a15+]2,%d15 # clear one halfword
286 ld.h %d14,[%a15+]2 # copy one halfword
/openbmc/linux/arch/arm/kernel/
H A Dphys2virt.S79 @ second halfword of the opcode (the 16-bit immediate is encoded
90 @ need to inspect the first halfword of the opcode, to check whether
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef556 "Vector halfword multiply, accumulate pairs, sat to word",
563 "Vector halfword multiply, accumulate pairs, sat to word",
573 "Vector halfword multiply, accumulate pairs, saturate to word",
580 "Vector halfword multiply, accumulate pairs, saturate to word",
611 "Vector halfword multiply, accumulate pairs, saturate to word",
618 "Vector halfword multiply, accumulate pairs, saturate to word",
937 V_SHIFT(h, "halfword", 16,4,2_2)
1089 "Vector shift add halfword",
1093 "Vector shift add halfword",
1381 "Vector halfword multiply with round, shift, and sat16",
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx-reference-design.dtsi68 intel,ixp4xx-eb-byte-access-on-halfword = <0>;
H A Dintel-ixp42x-arcom-vulcan.dts56 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
H A Dintel-ixp42x-gateworks-gw2348.dts95 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
H A Dintel-ixp43x-gateworks-gw2358.dts111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
/openbmc/linux/drivers/s390/scsi/
H A Dzfcp_fsf.h306 u16 halfword[FSF_STATUS_QUALIFIER_SIZE / sizeof (u16)]; member
/openbmc/qemu/target/arm/tcg/
H A Dt16.decode98 # Load/store halfword (immediate offset)
H A Dmve.decode162 # signed halfword element in register", etc.
/openbmc/qemu/target/hexagon/imported/
H A Dalu.idef50 COND_ALU(A4_psxth,"Rd32=sxth(Rs32)","Conditionally sign-extend halfword", RdV=fSXTN(16,32,RsV))
51 COND_ALU(A4_pzxth,"Rd32=zxth(Rs32)","Conditionally zero-extend halfword", RdV=fZXTN(16,32,RsV))
52 COND_ALU(A4_paslh,"Rd32=aslh(Rs32)","Conditionally zero-extend halfword", RdV=RsV<<16)
53 COND_ALU(A4_pasrh,"Rd32=asrh(Rs32)","Conditionally zero-extend halfword", RdV=RsV>>16)
/openbmc/u-boot/doc/imx/mkimage/
H A Dimximage.txt115 type: word=4, halfword=2, byte=1
/openbmc/linux/arch/mips/include/uapi/asm/
H A Dinst.h1117 unsigned short halfword[2]; member
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc1721 /* swapped unsigned halfword load with upper bits zeroed */
1730 /* swapped sign-extended halfword load */
/openbmc/qemu/target/mips/tcg/
H A Dmicromips_translate.c.inc2978 /* make sure instructions are on a halfword boundary */
H A Dnanomips_translate.c.inc4477 /* make sure instructions are on a halfword boundary */
/openbmc/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc2923 * Signed/Unsigned add/sub helper ops for byte/halfword/word