Home
last modified time | relevance | path

Searched refs:gpll (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drockchip,px30-cru.yaml55 - const: gpll
115 clock-names = "xin24m", "gpll";
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c132 u32 apllb, aplll, dpll, cpll, gpll; in rkclk_init() local
149 gpll = rkclk_pll_get_rate(cru, GPLL); in rkclk_init()
152 __func__, apllb, aplll, dpll, cpll, gpll); in rkclk_init()
H A Dclk_rv1108.c631 unsigned int apll, dpll, gpll; in rkclk_init() local
651 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); in rkclk_init()
656 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); in rkclk_init()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3036.c21 apll, dpll, gpll, enumerator
141 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
H A Dclk-rk3188.c19 apll, cpll, dpll, gpll, enumerator
222 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
233 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
H A Dclk-rk3128.c18 apll, dpll, cpll, gpll, enumerator
165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
H A Dclk-rk3228.c19 apll, dpll, cpll, gpll, enumerator
175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
H A Dclk-rk3328.c21 apll, dpll, cpll, gpll, npll, enumerator
224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
H A Dclk-rv1108.c19 apll, dpll, gpll, enumerator
158 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
H A Dclk-rk3368.c17 apllb, aplll, dpll, cpll, gpll, npll, enumerator
138 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
H A Dclk-rk3288.c24 apll, dpll, cpll, gpll, npll, enumerator
232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
H A Dclk-px30.c22 gpll, enumerator
200 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 0, PX30_PMU_PLL_CON(0),
H A Dclk-rv1126.c24 gpll, enumerator
191 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
H A Dclk-rk3399.c19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
227 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
H A Dclk-rk3568.c23 apll, dpll, gpll, cpll, npll, vpll, enumerator
332 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
H A Dclk-rk3588.c41 b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll, enumerator
686 [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
/openbmc/linux/drivers/clk/samsung/
H A Dclk-exynos5250.c108 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator
742 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
/openbmc/linux/drivers/clk/sprd/
H A Dums512-clk.c341 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x48, 3,
343 static CLK_FIXED_FACTOR_HW(gpll_40m, "gpll-40m", &gpll.common.hw,
356 &gpll.common,
391 [CLK_GPLL] = &gpll.common.hw,
1715 { .hw = &gpll.common.hw },
H A Dsc9863a-clk.c144 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x38, 3, itable,
155 &gpll.common,
184 [CLK_GPLL] = &gpll.common.hw,
548 { .hw = &gpll.common.hw },
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi834 clock-names = "xin24m", "gpll";