1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Pinctrl data for the NVIDIA Tegra114 pinmux
4  *
5  * Author: Pritesh Raithatha <praithatha@nvidia.com>
6  *
7  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
8  */
9 
10 #include <linux/init.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/pinctrl/pinctrl.h>
14 #include <linux/pinctrl/pinmux.h>
15 
16 #include "pinctrl-tegra.h"
17 
18 /*
19  * Most pins affected by the pinmux can also be GPIOs. Define these first.
20  * These must match how the GPIO driver names/numbers its pins.
21  */
22 #define _GPIO(offset)				(offset)
23 
24 #define TEGRA_PIN_CLK_32K_OUT_PA0		_GPIO(0)
25 #define TEGRA_PIN_UART3_CTS_N_PA1		_GPIO(1)
26 #define TEGRA_PIN_DAP2_FS_PA2			_GPIO(2)
27 #define TEGRA_PIN_DAP2_SCLK_PA3			_GPIO(3)
28 #define TEGRA_PIN_DAP2_DIN_PA4			_GPIO(4)
29 #define TEGRA_PIN_DAP2_DOUT_PA5			_GPIO(5)
30 #define TEGRA_PIN_SDMMC3_CLK_PA6		_GPIO(6)
31 #define TEGRA_PIN_SDMMC3_CMD_PA7		_GPIO(7)
32 #define TEGRA_PIN_GMI_A17_PB0			_GPIO(8)
33 #define TEGRA_PIN_GMI_A18_PB1			_GPIO(9)
34 #define TEGRA_PIN_SDMMC3_DAT3_PB4		_GPIO(12)
35 #define TEGRA_PIN_SDMMC3_DAT2_PB5		_GPIO(13)
36 #define TEGRA_PIN_SDMMC3_DAT1_PB6		_GPIO(14)
37 #define TEGRA_PIN_SDMMC3_DAT0_PB7		_GPIO(15)
38 #define TEGRA_PIN_UART3_RTS_N_PC0		_GPIO(16)
39 #define TEGRA_PIN_UART2_TXD_PC2			_GPIO(18)
40 #define TEGRA_PIN_UART2_RXD_PC3			_GPIO(19)
41 #define TEGRA_PIN_GEN1_I2C_SCL_PC4		_GPIO(20)
42 #define TEGRA_PIN_GEN1_I2C_SDA_PC5		_GPIO(21)
43 #define TEGRA_PIN_GMI_WP_N_PC7			_GPIO(23)
44 #define TEGRA_PIN_GMI_AD0_PG0			_GPIO(48)
45 #define TEGRA_PIN_GMI_AD1_PG1			_GPIO(49)
46 #define TEGRA_PIN_GMI_AD2_PG2			_GPIO(50)
47 #define TEGRA_PIN_GMI_AD3_PG3			_GPIO(51)
48 #define TEGRA_PIN_GMI_AD4_PG4			_GPIO(52)
49 #define TEGRA_PIN_GMI_AD5_PG5			_GPIO(53)
50 #define TEGRA_PIN_GMI_AD6_PG6			_GPIO(54)
51 #define TEGRA_PIN_GMI_AD7_PG7			_GPIO(55)
52 #define TEGRA_PIN_GMI_AD8_PH0			_GPIO(56)
53 #define TEGRA_PIN_GMI_AD9_PH1			_GPIO(57)
54 #define TEGRA_PIN_GMI_AD10_PH2			_GPIO(58)
55 #define TEGRA_PIN_GMI_AD11_PH3			_GPIO(59)
56 #define TEGRA_PIN_GMI_AD12_PH4			_GPIO(60)
57 #define TEGRA_PIN_GMI_AD13_PH5			_GPIO(61)
58 #define TEGRA_PIN_GMI_AD14_PH6			_GPIO(62)
59 #define TEGRA_PIN_GMI_AD15_PH7			_GPIO(63)
60 #define TEGRA_PIN_GMI_WR_N_PI0			_GPIO(64)
61 #define TEGRA_PIN_GMI_OE_N_PI1			_GPIO(65)
62 #define TEGRA_PIN_GMI_CS6_N_PI3			_GPIO(67)
63 #define TEGRA_PIN_GMI_RST_N_PI4			_GPIO(68)
64 #define TEGRA_PIN_GMI_IORDY_PI5			_GPIO(69)
65 #define TEGRA_PIN_GMI_CS7_N_PI6			_GPIO(70)
66 #define TEGRA_PIN_GMI_WAIT_PI7			_GPIO(71)
67 #define TEGRA_PIN_GMI_CS0_N_PJ0			_GPIO(72)
68 #define TEGRA_PIN_GMI_CS1_N_PJ2			_GPIO(74)
69 #define TEGRA_PIN_GMI_DQS_P_PJ3			_GPIO(75)
70 #define TEGRA_PIN_UART2_CTS_N_PJ5		_GPIO(77)
71 #define TEGRA_PIN_UART2_RTS_N_PJ6		_GPIO(78)
72 #define TEGRA_PIN_GMI_A16_PJ7			_GPIO(79)
73 #define TEGRA_PIN_GMI_ADV_N_PK0			_GPIO(80)
74 #define TEGRA_PIN_GMI_CLK_PK1			_GPIO(81)
75 #define TEGRA_PIN_GMI_CS4_N_PK2			_GPIO(82)
76 #define TEGRA_PIN_GMI_CS2_N_PK3			_GPIO(83)
77 #define TEGRA_PIN_GMI_CS3_N_PK4			_GPIO(84)
78 #define TEGRA_PIN_SPDIF_OUT_PK5			_GPIO(85)
79 #define TEGRA_PIN_SPDIF_IN_PK6			_GPIO(86)
80 #define TEGRA_PIN_GMI_A19_PK7			_GPIO(87)
81 #define TEGRA_PIN_DAP1_FS_PN0			_GPIO(104)
82 #define TEGRA_PIN_DAP1_DIN_PN1			_GPIO(105)
83 #define TEGRA_PIN_DAP1_DOUT_PN2			_GPIO(106)
84 #define TEGRA_PIN_DAP1_SCLK_PN3			_GPIO(107)
85 #define TEGRA_PIN_USB_VBUS_EN0_PN4		_GPIO(108)
86 #define TEGRA_PIN_USB_VBUS_EN1_PN5		_GPIO(109)
87 #define TEGRA_PIN_HDMI_INT_PN7			_GPIO(111)
88 #define TEGRA_PIN_ULPI_DATA7_PO0		_GPIO(112)
89 #define TEGRA_PIN_ULPI_DATA0_PO1		_GPIO(113)
90 #define TEGRA_PIN_ULPI_DATA1_PO2		_GPIO(114)
91 #define TEGRA_PIN_ULPI_DATA2_PO3		_GPIO(115)
92 #define TEGRA_PIN_ULPI_DATA3_PO4		_GPIO(116)
93 #define TEGRA_PIN_ULPI_DATA4_PO5		_GPIO(117)
94 #define TEGRA_PIN_ULPI_DATA5_PO6		_GPIO(118)
95 #define TEGRA_PIN_ULPI_DATA6_PO7		_GPIO(119)
96 #define TEGRA_PIN_DAP3_FS_PP0			_GPIO(120)
97 #define TEGRA_PIN_DAP3_DIN_PP1			_GPIO(121)
98 #define TEGRA_PIN_DAP3_DOUT_PP2			_GPIO(122)
99 #define TEGRA_PIN_DAP3_SCLK_PP3			_GPIO(123)
100 #define TEGRA_PIN_DAP4_FS_PP4			_GPIO(124)
101 #define TEGRA_PIN_DAP4_DIN_PP5			_GPIO(125)
102 #define TEGRA_PIN_DAP4_DOUT_PP6			_GPIO(126)
103 #define TEGRA_PIN_DAP4_SCLK_PP7			_GPIO(127)
104 #define TEGRA_PIN_KB_COL0_PQ0			_GPIO(128)
105 #define TEGRA_PIN_KB_COL1_PQ1			_GPIO(129)
106 #define TEGRA_PIN_KB_COL2_PQ2			_GPIO(130)
107 #define TEGRA_PIN_KB_COL3_PQ3			_GPIO(131)
108 #define TEGRA_PIN_KB_COL4_PQ4			_GPIO(132)
109 #define TEGRA_PIN_KB_COL5_PQ5			_GPIO(133)
110 #define TEGRA_PIN_KB_COL6_PQ6			_GPIO(134)
111 #define TEGRA_PIN_KB_COL7_PQ7			_GPIO(135)
112 #define TEGRA_PIN_KB_ROW0_PR0			_GPIO(136)
113 #define TEGRA_PIN_KB_ROW1_PR1			_GPIO(137)
114 #define TEGRA_PIN_KB_ROW2_PR2			_GPIO(138)
115 #define TEGRA_PIN_KB_ROW3_PR3			_GPIO(139)
116 #define TEGRA_PIN_KB_ROW4_PR4			_GPIO(140)
117 #define TEGRA_PIN_KB_ROW5_PR5			_GPIO(141)
118 #define TEGRA_PIN_KB_ROW6_PR6			_GPIO(142)
119 #define TEGRA_PIN_KB_ROW7_PR7			_GPIO(143)
120 #define TEGRA_PIN_KB_ROW8_PS0			_GPIO(144)
121 #define TEGRA_PIN_KB_ROW9_PS1			_GPIO(145)
122 #define TEGRA_PIN_KB_ROW10_PS2			_GPIO(146)
123 #define TEGRA_PIN_GEN2_I2C_SCL_PT5		_GPIO(157)
124 #define TEGRA_PIN_GEN2_I2C_SDA_PT6		_GPIO(158)
125 #define TEGRA_PIN_SDMMC4_CMD_PT7		_GPIO(159)
126 #define TEGRA_PIN_PU0				_GPIO(160)
127 #define TEGRA_PIN_PU1				_GPIO(161)
128 #define TEGRA_PIN_PU2				_GPIO(162)
129 #define TEGRA_PIN_PU3				_GPIO(163)
130 #define TEGRA_PIN_PU4				_GPIO(164)
131 #define TEGRA_PIN_PU5				_GPIO(165)
132 #define TEGRA_PIN_PU6				_GPIO(166)
133 #define TEGRA_PIN_PV0				_GPIO(168)
134 #define TEGRA_PIN_PV1				_GPIO(169)
135 #define TEGRA_PIN_SDMMC3_CD_N_PV2		_GPIO(170)
136 #define TEGRA_PIN_SDMMC1_WP_N_PV3		_GPIO(171)
137 #define TEGRA_PIN_DDC_SCL_PV4			_GPIO(172)
138 #define TEGRA_PIN_DDC_SDA_PV5			_GPIO(173)
139 #define TEGRA_PIN_GPIO_W2_AUD_PW2		_GPIO(178)
140 #define TEGRA_PIN_GPIO_W3_AUD_PW3		_GPIO(179)
141 #define TEGRA_PIN_CLK1_OUT_PW4			_GPIO(180)
142 #define TEGRA_PIN_CLK2_OUT_PW5			_GPIO(181)
143 #define TEGRA_PIN_UART3_TXD_PW6			_GPIO(182)
144 #define TEGRA_PIN_UART3_RXD_PW7			_GPIO(183)
145 #define TEGRA_PIN_DVFS_PWM_PX0			_GPIO(184)
146 #define TEGRA_PIN_GPIO_X1_AUD_PX1		_GPIO(185)
147 #define TEGRA_PIN_DVFS_CLK_PX2			_GPIO(186)
148 #define TEGRA_PIN_GPIO_X3_AUD_PX3		_GPIO(187)
149 #define TEGRA_PIN_GPIO_X4_AUD_PX4		_GPIO(188)
150 #define TEGRA_PIN_GPIO_X5_AUD_PX5		_GPIO(189)
151 #define TEGRA_PIN_GPIO_X6_AUD_PX6		_GPIO(190)
152 #define TEGRA_PIN_GPIO_X7_AUD_PX7		_GPIO(191)
153 #define TEGRA_PIN_ULPI_CLK_PY0			_GPIO(192)
154 #define TEGRA_PIN_ULPI_DIR_PY1			_GPIO(193)
155 #define TEGRA_PIN_ULPI_NXT_PY2			_GPIO(194)
156 #define TEGRA_PIN_ULPI_STP_PY3			_GPIO(195)
157 #define TEGRA_PIN_SDMMC1_DAT3_PY4		_GPIO(196)
158 #define TEGRA_PIN_SDMMC1_DAT2_PY5		_GPIO(197)
159 #define TEGRA_PIN_SDMMC1_DAT1_PY6		_GPIO(198)
160 #define TEGRA_PIN_SDMMC1_DAT0_PY7		_GPIO(199)
161 #define TEGRA_PIN_SDMMC1_CLK_PZ0		_GPIO(200)
162 #define TEGRA_PIN_SDMMC1_CMD_PZ1		_GPIO(201)
163 #define TEGRA_PIN_SYS_CLK_REQ_PZ5		_GPIO(205)
164 #define TEGRA_PIN_PWR_I2C_SCL_PZ6		_GPIO(206)
165 #define TEGRA_PIN_PWR_I2C_SDA_PZ7		_GPIO(207)
166 #define TEGRA_PIN_SDMMC4_DAT0_PAA0		_GPIO(208)
167 #define TEGRA_PIN_SDMMC4_DAT1_PAA1		_GPIO(209)
168 #define TEGRA_PIN_SDMMC4_DAT2_PAA2		_GPIO(210)
169 #define TEGRA_PIN_SDMMC4_DAT3_PAA3		_GPIO(211)
170 #define TEGRA_PIN_SDMMC4_DAT4_PAA4		_GPIO(212)
171 #define TEGRA_PIN_SDMMC4_DAT5_PAA5		_GPIO(213)
172 #define TEGRA_PIN_SDMMC4_DAT6_PAA6		_GPIO(214)
173 #define TEGRA_PIN_SDMMC4_DAT7_PAA7		_GPIO(215)
174 #define TEGRA_PIN_PBB0				_GPIO(216)
175 #define TEGRA_PIN_CAM_I2C_SCL_PBB1		_GPIO(217)
176 #define TEGRA_PIN_CAM_I2C_SDA_PBB2		_GPIO(218)
177 #define TEGRA_PIN_PBB3				_GPIO(219)
178 #define TEGRA_PIN_PBB4				_GPIO(220)
179 #define TEGRA_PIN_PBB5				_GPIO(221)
180 #define TEGRA_PIN_PBB6				_GPIO(222)
181 #define TEGRA_PIN_PBB7				_GPIO(223)
182 #define TEGRA_PIN_CAM_MCLK_PCC0			_GPIO(224)
183 #define TEGRA_PIN_PCC1				_GPIO(225)
184 #define TEGRA_PIN_PCC2				_GPIO(226)
185 #define TEGRA_PIN_SDMMC4_CLK_PCC4		_GPIO(228)
186 #define TEGRA_PIN_CLK2_REQ_PCC5			_GPIO(229)
187 #define TEGRA_PIN_CLK3_OUT_PEE0			_GPIO(240)
188 #define TEGRA_PIN_CLK3_REQ_PEE1			_GPIO(241)
189 #define TEGRA_PIN_CLK1_REQ_PEE2			_GPIO(242)
190 #define TEGRA_PIN_HDMI_CEC_PEE3			_GPIO(243)
191 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4	_GPIO(244)
192 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5		_GPIO(245)
193 
194 /* All non-GPIO pins follow */
195 #define NUM_GPIOS				(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
196 #define _PIN(offset)				(NUM_GPIOS + (offset))
197 
198 /* Non-GPIO pins */
199 #define TEGRA_PIN_CORE_PWR_REQ			_PIN(0)
200 #define TEGRA_PIN_CPU_PWR_REQ			_PIN(1)
201 #define TEGRA_PIN_PWR_INT_N			_PIN(2)
202 #define TEGRA_PIN_RESET_OUT_N			_PIN(3)
203 #define TEGRA_PIN_OWR				_PIN(4)
204 #define TEGRA_PIN_JTAG_RTCK			_PIN(5)
205 #define TEGRA_PIN_CLK_32K_IN			_PIN(6)
206 #define TEGRA_PIN_GMI_CLK_LB			_PIN(7)
207 
208 static const struct pinctrl_pin_desc tegra114_pins[] = {
209 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
210 	PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
211 	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
212 	PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
213 	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
214 	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
215 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
216 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
217 	PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
218 	PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
219 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
220 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
221 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
222 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
223 	PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
224 	PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
225 	PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
226 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
227 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
228 	PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
229 	PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
230 	PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
231 	PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
232 	PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
233 	PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
234 	PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
235 	PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
236 	PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
237 	PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
238 	PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
239 	PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
240 	PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
241 	PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
242 	PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
243 	PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
244 	PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
245 	PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
246 	PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
247 	PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
248 	PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
249 	PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
250 	PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
251 	PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
252 	PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
253 	PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
254 	PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
255 	PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
256 	PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
257 	PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
258 	PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
259 	PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
260 	PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
261 	PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
262 	PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
263 	PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
264 	PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
265 	PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
266 	PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
267 	PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
268 	PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
269 	PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
270 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
271 	PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
272 	PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
273 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
274 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
275 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
276 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
277 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
278 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
279 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
280 	PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
281 	PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
282 	PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
283 	PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
284 	PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
285 	PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
286 	PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
287 	PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
288 	PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
289 	PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
290 	PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
291 	PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
292 	PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
293 	PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
294 	PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
295 	PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
296 	PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
297 	PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
298 	PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
299 	PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
300 	PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
301 	PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
302 	PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
303 	PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
304 	PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
305 	PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
306 	PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
307 	PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
308 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
309 	PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
310 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
311 	PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
312 	PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
313 	PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
314 	PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
315 	PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
316 	PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
317 	PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
318 	PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
319 	PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
320 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
321 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
322 	PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
323 	PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
324 	PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
325 	PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
326 	PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
327 	PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
328 	PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
329 	PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
330 	PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
331 	PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
332 	PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
333 	PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
334 	PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
335 	PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
336 	PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
337 	PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
338 	PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
339 	PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
340 	PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
341 	PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
342 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
343 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
344 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
345 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
346 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
347 	PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
348 	PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
349 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
350 	PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
351 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
352 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
353 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
354 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
355 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
356 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
357 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
358 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
359 	PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
360 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
361 	PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
362 	PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
363 	PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
364 	PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
365 	PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
366 	PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
367 	PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
368 	PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
369 	PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
370 	PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
371 	PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
372 	PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
373 	PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
374 	PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
375 	PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
376 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
377 	PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
378 	PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
379 	PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
380 	PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
381 	PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
382 	PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
383 	PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
384 	PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
385 	PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
386 };
387 
388 static const unsigned clk_32k_out_pa0_pins[] = {
389 	TEGRA_PIN_CLK_32K_OUT_PA0,
390 };
391 
392 static const unsigned uart3_cts_n_pa1_pins[] = {
393 	TEGRA_PIN_UART3_CTS_N_PA1,
394 };
395 
396 static const unsigned dap2_fs_pa2_pins[] = {
397 	TEGRA_PIN_DAP2_FS_PA2,
398 };
399 
400 static const unsigned dap2_sclk_pa3_pins[] = {
401 	TEGRA_PIN_DAP2_SCLK_PA3,
402 };
403 
404 static const unsigned dap2_din_pa4_pins[] = {
405 	TEGRA_PIN_DAP2_DIN_PA4,
406 };
407 
408 static const unsigned dap2_dout_pa5_pins[] = {
409 	TEGRA_PIN_DAP2_DOUT_PA5,
410 };
411 
412 static const unsigned sdmmc3_clk_pa6_pins[] = {
413 	TEGRA_PIN_SDMMC3_CLK_PA6,
414 };
415 
416 static const unsigned sdmmc3_cmd_pa7_pins[] = {
417 	TEGRA_PIN_SDMMC3_CMD_PA7,
418 };
419 
420 static const unsigned gmi_a17_pb0_pins[] = {
421 	TEGRA_PIN_GMI_A17_PB0,
422 };
423 
424 static const unsigned gmi_a18_pb1_pins[] = {
425 	TEGRA_PIN_GMI_A18_PB1,
426 };
427 
428 static const unsigned sdmmc3_dat3_pb4_pins[] = {
429 	TEGRA_PIN_SDMMC3_DAT3_PB4,
430 };
431 
432 static const unsigned sdmmc3_dat2_pb5_pins[] = {
433 	TEGRA_PIN_SDMMC3_DAT2_PB5,
434 };
435 
436 static const unsigned sdmmc3_dat1_pb6_pins[] = {
437 	TEGRA_PIN_SDMMC3_DAT1_PB6,
438 };
439 
440 static const unsigned sdmmc3_dat0_pb7_pins[] = {
441 	TEGRA_PIN_SDMMC3_DAT0_PB7,
442 };
443 
444 static const unsigned uart3_rts_n_pc0_pins[] = {
445 	TEGRA_PIN_UART3_RTS_N_PC0,
446 };
447 
448 static const unsigned uart2_txd_pc2_pins[] = {
449 	TEGRA_PIN_UART2_TXD_PC2,
450 };
451 
452 static const unsigned uart2_rxd_pc3_pins[] = {
453 	TEGRA_PIN_UART2_RXD_PC3,
454 };
455 
456 static const unsigned gen1_i2c_scl_pc4_pins[] = {
457 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
458 };
459 
460 static const unsigned gen1_i2c_sda_pc5_pins[] = {
461 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
462 };
463 
464 static const unsigned gmi_wp_n_pc7_pins[] = {
465 	TEGRA_PIN_GMI_WP_N_PC7,
466 };
467 
468 static const unsigned gmi_ad0_pg0_pins[] = {
469 	TEGRA_PIN_GMI_AD0_PG0,
470 };
471 
472 static const unsigned gmi_ad1_pg1_pins[] = {
473 	TEGRA_PIN_GMI_AD1_PG1,
474 };
475 
476 static const unsigned gmi_ad2_pg2_pins[] = {
477 	TEGRA_PIN_GMI_AD2_PG2,
478 };
479 
480 static const unsigned gmi_ad3_pg3_pins[] = {
481 	TEGRA_PIN_GMI_AD3_PG3,
482 };
483 
484 static const unsigned gmi_ad4_pg4_pins[] = {
485 	TEGRA_PIN_GMI_AD4_PG4,
486 };
487 
488 static const unsigned gmi_ad5_pg5_pins[] = {
489 	TEGRA_PIN_GMI_AD5_PG5,
490 };
491 
492 static const unsigned gmi_ad6_pg6_pins[] = {
493 	TEGRA_PIN_GMI_AD6_PG6,
494 };
495 
496 static const unsigned gmi_ad7_pg7_pins[] = {
497 	TEGRA_PIN_GMI_AD7_PG7,
498 };
499 
500 static const unsigned gmi_ad8_ph0_pins[] = {
501 	TEGRA_PIN_GMI_AD8_PH0,
502 };
503 
504 static const unsigned gmi_ad9_ph1_pins[] = {
505 	TEGRA_PIN_GMI_AD9_PH1,
506 };
507 
508 static const unsigned gmi_ad10_ph2_pins[] = {
509 	TEGRA_PIN_GMI_AD10_PH2,
510 };
511 
512 static const unsigned gmi_ad11_ph3_pins[] = {
513 	TEGRA_PIN_GMI_AD11_PH3,
514 };
515 
516 static const unsigned gmi_ad12_ph4_pins[] = {
517 	TEGRA_PIN_GMI_AD12_PH4,
518 };
519 
520 static const unsigned gmi_ad13_ph5_pins[] = {
521 	TEGRA_PIN_GMI_AD13_PH5,
522 };
523 
524 static const unsigned gmi_ad14_ph6_pins[] = {
525 	TEGRA_PIN_GMI_AD14_PH6,
526 };
527 
528 static const unsigned gmi_ad15_ph7_pins[] = {
529 	TEGRA_PIN_GMI_AD15_PH7,
530 };
531 
532 static const unsigned gmi_wr_n_pi0_pins[] = {
533 	TEGRA_PIN_GMI_WR_N_PI0,
534 };
535 
536 static const unsigned gmi_oe_n_pi1_pins[] = {
537 	TEGRA_PIN_GMI_OE_N_PI1,
538 };
539 
540 static const unsigned gmi_cs6_n_pi3_pins[] = {
541 	TEGRA_PIN_GMI_CS6_N_PI3,
542 };
543 
544 static const unsigned gmi_rst_n_pi4_pins[] = {
545 	TEGRA_PIN_GMI_RST_N_PI4,
546 };
547 
548 static const unsigned gmi_iordy_pi5_pins[] = {
549 	TEGRA_PIN_GMI_IORDY_PI5,
550 };
551 
552 static const unsigned gmi_cs7_n_pi6_pins[] = {
553 	TEGRA_PIN_GMI_CS7_N_PI6,
554 };
555 
556 static const unsigned gmi_wait_pi7_pins[] = {
557 	TEGRA_PIN_GMI_WAIT_PI7,
558 };
559 
560 static const unsigned gmi_cs0_n_pj0_pins[] = {
561 	TEGRA_PIN_GMI_CS0_N_PJ0,
562 };
563 
564 static const unsigned gmi_cs1_n_pj2_pins[] = {
565 	TEGRA_PIN_GMI_CS1_N_PJ2,
566 };
567 
568 static const unsigned gmi_dqs_p_pj3_pins[] = {
569 	TEGRA_PIN_GMI_DQS_P_PJ3,
570 };
571 
572 static const unsigned uart2_cts_n_pj5_pins[] = {
573 	TEGRA_PIN_UART2_CTS_N_PJ5,
574 };
575 
576 static const unsigned uart2_rts_n_pj6_pins[] = {
577 	TEGRA_PIN_UART2_RTS_N_PJ6,
578 };
579 
580 static const unsigned gmi_a16_pj7_pins[] = {
581 	TEGRA_PIN_GMI_A16_PJ7,
582 };
583 
584 static const unsigned gmi_adv_n_pk0_pins[] = {
585 	TEGRA_PIN_GMI_ADV_N_PK0,
586 };
587 
588 static const unsigned gmi_clk_pk1_pins[] = {
589 	TEGRA_PIN_GMI_CLK_PK1,
590 };
591 
592 static const unsigned gmi_cs4_n_pk2_pins[] = {
593 	TEGRA_PIN_GMI_CS4_N_PK2,
594 };
595 
596 static const unsigned gmi_cs2_n_pk3_pins[] = {
597 	TEGRA_PIN_GMI_CS2_N_PK3,
598 };
599 
600 static const unsigned gmi_cs3_n_pk4_pins[] = {
601 	TEGRA_PIN_GMI_CS3_N_PK4,
602 };
603 
604 static const unsigned spdif_out_pk5_pins[] = {
605 	TEGRA_PIN_SPDIF_OUT_PK5,
606 };
607 
608 static const unsigned spdif_in_pk6_pins[] = {
609 	TEGRA_PIN_SPDIF_IN_PK6,
610 };
611 
612 static const unsigned gmi_a19_pk7_pins[] = {
613 	TEGRA_PIN_GMI_A19_PK7,
614 };
615 
616 static const unsigned dap1_fs_pn0_pins[] = {
617 	TEGRA_PIN_DAP1_FS_PN0,
618 };
619 
620 static const unsigned dap1_din_pn1_pins[] = {
621 	TEGRA_PIN_DAP1_DIN_PN1,
622 };
623 
624 static const unsigned dap1_dout_pn2_pins[] = {
625 	TEGRA_PIN_DAP1_DOUT_PN2,
626 };
627 
628 static const unsigned dap1_sclk_pn3_pins[] = {
629 	TEGRA_PIN_DAP1_SCLK_PN3,
630 };
631 
632 static const unsigned usb_vbus_en0_pn4_pins[] = {
633 	TEGRA_PIN_USB_VBUS_EN0_PN4,
634 };
635 
636 static const unsigned usb_vbus_en1_pn5_pins[] = {
637 	TEGRA_PIN_USB_VBUS_EN1_PN5,
638 };
639 
640 static const unsigned hdmi_int_pn7_pins[] = {
641 	TEGRA_PIN_HDMI_INT_PN7,
642 };
643 
644 static const unsigned ulpi_data7_po0_pins[] = {
645 	TEGRA_PIN_ULPI_DATA7_PO0,
646 };
647 
648 static const unsigned ulpi_data0_po1_pins[] = {
649 	TEGRA_PIN_ULPI_DATA0_PO1,
650 };
651 
652 static const unsigned ulpi_data1_po2_pins[] = {
653 	TEGRA_PIN_ULPI_DATA1_PO2,
654 };
655 
656 static const unsigned ulpi_data2_po3_pins[] = {
657 	TEGRA_PIN_ULPI_DATA2_PO3,
658 };
659 
660 static const unsigned ulpi_data3_po4_pins[] = {
661 	TEGRA_PIN_ULPI_DATA3_PO4,
662 };
663 
664 static const unsigned ulpi_data4_po5_pins[] = {
665 	TEGRA_PIN_ULPI_DATA4_PO5,
666 };
667 
668 static const unsigned ulpi_data5_po6_pins[] = {
669 	TEGRA_PIN_ULPI_DATA5_PO6,
670 };
671 
672 static const unsigned ulpi_data6_po7_pins[] = {
673 	TEGRA_PIN_ULPI_DATA6_PO7,
674 };
675 
676 static const unsigned dap3_fs_pp0_pins[] = {
677 	TEGRA_PIN_DAP3_FS_PP0,
678 };
679 
680 static const unsigned dap3_din_pp1_pins[] = {
681 	TEGRA_PIN_DAP3_DIN_PP1,
682 };
683 
684 static const unsigned dap3_dout_pp2_pins[] = {
685 	TEGRA_PIN_DAP3_DOUT_PP2,
686 };
687 
688 static const unsigned dap3_sclk_pp3_pins[] = {
689 	TEGRA_PIN_DAP3_SCLK_PP3,
690 };
691 
692 static const unsigned dap4_fs_pp4_pins[] = {
693 	TEGRA_PIN_DAP4_FS_PP4,
694 };
695 
696 static const unsigned dap4_din_pp5_pins[] = {
697 	TEGRA_PIN_DAP4_DIN_PP5,
698 };
699 
700 static const unsigned dap4_dout_pp6_pins[] = {
701 	TEGRA_PIN_DAP4_DOUT_PP6,
702 };
703 
704 static const unsigned dap4_sclk_pp7_pins[] = {
705 	TEGRA_PIN_DAP4_SCLK_PP7,
706 };
707 
708 static const unsigned kb_col0_pq0_pins[] = {
709 	TEGRA_PIN_KB_COL0_PQ0,
710 };
711 
712 static const unsigned kb_col1_pq1_pins[] = {
713 	TEGRA_PIN_KB_COL1_PQ1,
714 };
715 
716 static const unsigned kb_col2_pq2_pins[] = {
717 	TEGRA_PIN_KB_COL2_PQ2,
718 };
719 
720 static const unsigned kb_col3_pq3_pins[] = {
721 	TEGRA_PIN_KB_COL3_PQ3,
722 };
723 
724 static const unsigned kb_col4_pq4_pins[] = {
725 	TEGRA_PIN_KB_COL4_PQ4,
726 };
727 
728 static const unsigned kb_col5_pq5_pins[] = {
729 	TEGRA_PIN_KB_COL5_PQ5,
730 };
731 
732 static const unsigned kb_col6_pq6_pins[] = {
733 	TEGRA_PIN_KB_COL6_PQ6,
734 };
735 
736 static const unsigned kb_col7_pq7_pins[] = {
737 	TEGRA_PIN_KB_COL7_PQ7,
738 };
739 
740 static const unsigned kb_row0_pr0_pins[] = {
741 	TEGRA_PIN_KB_ROW0_PR0,
742 };
743 
744 static const unsigned kb_row1_pr1_pins[] = {
745 	TEGRA_PIN_KB_ROW1_PR1,
746 };
747 
748 static const unsigned kb_row2_pr2_pins[] = {
749 	TEGRA_PIN_KB_ROW2_PR2,
750 };
751 
752 static const unsigned kb_row3_pr3_pins[] = {
753 	TEGRA_PIN_KB_ROW3_PR3,
754 };
755 
756 static const unsigned kb_row4_pr4_pins[] = {
757 	TEGRA_PIN_KB_ROW4_PR4,
758 };
759 
760 static const unsigned kb_row5_pr5_pins[] = {
761 	TEGRA_PIN_KB_ROW5_PR5,
762 };
763 
764 static const unsigned kb_row6_pr6_pins[] = {
765 	TEGRA_PIN_KB_ROW6_PR6,
766 };
767 
768 static const unsigned kb_row7_pr7_pins[] = {
769 	TEGRA_PIN_KB_ROW7_PR7,
770 };
771 
772 static const unsigned kb_row8_ps0_pins[] = {
773 	TEGRA_PIN_KB_ROW8_PS0,
774 };
775 
776 static const unsigned kb_row9_ps1_pins[] = {
777 	TEGRA_PIN_KB_ROW9_PS1,
778 };
779 
780 static const unsigned kb_row10_ps2_pins[] = {
781 	TEGRA_PIN_KB_ROW10_PS2,
782 };
783 
784 static const unsigned gen2_i2c_scl_pt5_pins[] = {
785 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
786 };
787 
788 static const unsigned gen2_i2c_sda_pt6_pins[] = {
789 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
790 };
791 
792 static const unsigned sdmmc4_cmd_pt7_pins[] = {
793 	TEGRA_PIN_SDMMC4_CMD_PT7,
794 };
795 
796 static const unsigned pu0_pins[] = {
797 	TEGRA_PIN_PU0,
798 };
799 
800 static const unsigned pu1_pins[] = {
801 	TEGRA_PIN_PU1,
802 };
803 
804 static const unsigned pu2_pins[] = {
805 	TEGRA_PIN_PU2,
806 };
807 
808 static const unsigned pu3_pins[] = {
809 	TEGRA_PIN_PU3,
810 };
811 
812 static const unsigned pu4_pins[] = {
813 	TEGRA_PIN_PU4,
814 };
815 
816 static const unsigned pu5_pins[] = {
817 	TEGRA_PIN_PU5,
818 };
819 
820 static const unsigned pu6_pins[] = {
821 	TEGRA_PIN_PU6,
822 };
823 
824 static const unsigned pv0_pins[] = {
825 	TEGRA_PIN_PV0,
826 };
827 
828 static const unsigned pv1_pins[] = {
829 	TEGRA_PIN_PV1,
830 };
831 
832 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
833 	TEGRA_PIN_SDMMC3_CD_N_PV2,
834 };
835 
836 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
837 	TEGRA_PIN_SDMMC1_WP_N_PV3,
838 };
839 
840 static const unsigned ddc_scl_pv4_pins[] = {
841 	TEGRA_PIN_DDC_SCL_PV4,
842 };
843 
844 static const unsigned ddc_sda_pv5_pins[] = {
845 	TEGRA_PIN_DDC_SDA_PV5,
846 };
847 
848 static const unsigned gpio_w2_aud_pw2_pins[] = {
849 	TEGRA_PIN_GPIO_W2_AUD_PW2,
850 };
851 
852 static const unsigned gpio_w3_aud_pw3_pins[] = {
853 	TEGRA_PIN_GPIO_W3_AUD_PW3,
854 };
855 
856 static const unsigned clk1_out_pw4_pins[] = {
857 	TEGRA_PIN_CLK1_OUT_PW4,
858 };
859 
860 static const unsigned clk2_out_pw5_pins[] = {
861 	TEGRA_PIN_CLK2_OUT_PW5,
862 };
863 
864 static const unsigned uart3_txd_pw6_pins[] = {
865 	TEGRA_PIN_UART3_TXD_PW6,
866 };
867 
868 static const unsigned uart3_rxd_pw7_pins[] = {
869 	TEGRA_PIN_UART3_RXD_PW7,
870 };
871 
872 static const unsigned dvfs_pwm_px0_pins[] = {
873 	TEGRA_PIN_DVFS_PWM_PX0,
874 };
875 
876 static const unsigned gpio_x1_aud_px1_pins[] = {
877 	TEGRA_PIN_GPIO_X1_AUD_PX1,
878 };
879 
880 static const unsigned dvfs_clk_px2_pins[] = {
881 	TEGRA_PIN_DVFS_CLK_PX2,
882 };
883 
884 static const unsigned gpio_x3_aud_px3_pins[] = {
885 	TEGRA_PIN_GPIO_X3_AUD_PX3,
886 };
887 
888 static const unsigned gpio_x4_aud_px4_pins[] = {
889 	TEGRA_PIN_GPIO_X4_AUD_PX4,
890 };
891 
892 static const unsigned gpio_x5_aud_px5_pins[] = {
893 	TEGRA_PIN_GPIO_X5_AUD_PX5,
894 };
895 
896 static const unsigned gpio_x6_aud_px6_pins[] = {
897 	TEGRA_PIN_GPIO_X6_AUD_PX6,
898 };
899 
900 static const unsigned gpio_x7_aud_px7_pins[] = {
901 	TEGRA_PIN_GPIO_X7_AUD_PX7,
902 };
903 
904 static const unsigned ulpi_clk_py0_pins[] = {
905 	TEGRA_PIN_ULPI_CLK_PY0,
906 };
907 
908 static const unsigned ulpi_dir_py1_pins[] = {
909 	TEGRA_PIN_ULPI_DIR_PY1,
910 };
911 
912 static const unsigned ulpi_nxt_py2_pins[] = {
913 	TEGRA_PIN_ULPI_NXT_PY2,
914 };
915 
916 static const unsigned ulpi_stp_py3_pins[] = {
917 	TEGRA_PIN_ULPI_STP_PY3,
918 };
919 
920 static const unsigned sdmmc1_dat3_py4_pins[] = {
921 	TEGRA_PIN_SDMMC1_DAT3_PY4,
922 };
923 
924 static const unsigned sdmmc1_dat2_py5_pins[] = {
925 	TEGRA_PIN_SDMMC1_DAT2_PY5,
926 };
927 
928 static const unsigned sdmmc1_dat1_py6_pins[] = {
929 	TEGRA_PIN_SDMMC1_DAT1_PY6,
930 };
931 
932 static const unsigned sdmmc1_dat0_py7_pins[] = {
933 	TEGRA_PIN_SDMMC1_DAT0_PY7,
934 };
935 
936 static const unsigned sdmmc1_clk_pz0_pins[] = {
937 	TEGRA_PIN_SDMMC1_CLK_PZ0,
938 };
939 
940 static const unsigned sdmmc1_cmd_pz1_pins[] = {
941 	TEGRA_PIN_SDMMC1_CMD_PZ1,
942 };
943 
944 static const unsigned sys_clk_req_pz5_pins[] = {
945 	TEGRA_PIN_SYS_CLK_REQ_PZ5,
946 };
947 
948 static const unsigned pwr_i2c_scl_pz6_pins[] = {
949 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
950 };
951 
952 static const unsigned pwr_i2c_sda_pz7_pins[] = {
953 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
954 };
955 
956 static const unsigned sdmmc4_dat0_paa0_pins[] = {
957 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
958 };
959 
960 static const unsigned sdmmc4_dat1_paa1_pins[] = {
961 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
962 };
963 
964 static const unsigned sdmmc4_dat2_paa2_pins[] = {
965 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
966 };
967 
968 static const unsigned sdmmc4_dat3_paa3_pins[] = {
969 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
970 };
971 
972 static const unsigned sdmmc4_dat4_paa4_pins[] = {
973 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
974 };
975 
976 static const unsigned sdmmc4_dat5_paa5_pins[] = {
977 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
978 };
979 
980 static const unsigned sdmmc4_dat6_paa6_pins[] = {
981 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
982 };
983 
984 static const unsigned sdmmc4_dat7_paa7_pins[] = {
985 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
986 };
987 
988 static const unsigned pbb0_pins[] = {
989 	TEGRA_PIN_PBB0,
990 };
991 
992 static const unsigned cam_i2c_scl_pbb1_pins[] = {
993 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
994 };
995 
996 static const unsigned cam_i2c_sda_pbb2_pins[] = {
997 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
998 };
999 
1000 static const unsigned pbb3_pins[] = {
1001 	TEGRA_PIN_PBB3,
1002 };
1003 
1004 static const unsigned pbb4_pins[] = {
1005 	TEGRA_PIN_PBB4,
1006 };
1007 
1008 static const unsigned pbb5_pins[] = {
1009 	TEGRA_PIN_PBB5,
1010 };
1011 
1012 static const unsigned pbb6_pins[] = {
1013 	TEGRA_PIN_PBB6,
1014 };
1015 
1016 static const unsigned pbb7_pins[] = {
1017 	TEGRA_PIN_PBB7,
1018 };
1019 
1020 static const unsigned cam_mclk_pcc0_pins[] = {
1021 	TEGRA_PIN_CAM_MCLK_PCC0,
1022 };
1023 
1024 static const unsigned pcc1_pins[] = {
1025 	TEGRA_PIN_PCC1,
1026 };
1027 
1028 static const unsigned pcc2_pins[] = {
1029 	TEGRA_PIN_PCC2,
1030 };
1031 
1032 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1033 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1034 };
1035 
1036 static const unsigned clk2_req_pcc5_pins[] = {
1037 	TEGRA_PIN_CLK2_REQ_PCC5,
1038 };
1039 
1040 static const unsigned clk3_out_pee0_pins[] = {
1041 	TEGRA_PIN_CLK3_OUT_PEE0,
1042 };
1043 
1044 static const unsigned clk3_req_pee1_pins[] = {
1045 	TEGRA_PIN_CLK3_REQ_PEE1,
1046 };
1047 
1048 static const unsigned clk1_req_pee2_pins[] = {
1049 	TEGRA_PIN_CLK1_REQ_PEE2,
1050 };
1051 
1052 static const unsigned hdmi_cec_pee3_pins[] = {
1053 	TEGRA_PIN_HDMI_CEC_PEE3,
1054 };
1055 
1056 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1057 	TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1058 };
1059 
1060 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1061 	TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1062 };
1063 
1064 static const unsigned core_pwr_req_pins[] = {
1065 	TEGRA_PIN_CORE_PWR_REQ,
1066 };
1067 
1068 static const unsigned cpu_pwr_req_pins[] = {
1069 	TEGRA_PIN_CPU_PWR_REQ,
1070 };
1071 
1072 static const unsigned pwr_int_n_pins[] = {
1073 	TEGRA_PIN_PWR_INT_N,
1074 };
1075 
1076 static const unsigned reset_out_n_pins[] = {
1077 	TEGRA_PIN_RESET_OUT_N,
1078 };
1079 
1080 static const unsigned owr_pins[] = {
1081 	TEGRA_PIN_OWR,
1082 };
1083 
1084 static const unsigned jtag_rtck_pins[] = {
1085 	TEGRA_PIN_JTAG_RTCK,
1086 };
1087 
1088 static const unsigned clk_32k_in_pins[] = {
1089 	TEGRA_PIN_CLK_32K_IN,
1090 };
1091 
1092 static const unsigned gmi_clk_lb_pins[] = {
1093 	TEGRA_PIN_GMI_CLK_LB,
1094 };
1095 
1096 static const unsigned drive_ao1_pins[] = {
1097 	TEGRA_PIN_KB_ROW0_PR0,
1098 	TEGRA_PIN_KB_ROW1_PR1,
1099 	TEGRA_PIN_KB_ROW2_PR2,
1100 	TEGRA_PIN_KB_ROW3_PR3,
1101 	TEGRA_PIN_KB_ROW4_PR4,
1102 	TEGRA_PIN_KB_ROW5_PR5,
1103 	TEGRA_PIN_KB_ROW6_PR6,
1104 	TEGRA_PIN_KB_ROW7_PR7,
1105 	TEGRA_PIN_PWR_I2C_SCL_PZ6,
1106 	TEGRA_PIN_PWR_I2C_SDA_PZ7,
1107 };
1108 
1109 static const unsigned drive_ao2_pins[] = {
1110 	TEGRA_PIN_CLK_32K_OUT_PA0,
1111 	TEGRA_PIN_KB_COL0_PQ0,
1112 	TEGRA_PIN_KB_COL1_PQ1,
1113 	TEGRA_PIN_KB_COL2_PQ2,
1114 	TEGRA_PIN_KB_COL3_PQ3,
1115 	TEGRA_PIN_KB_COL4_PQ4,
1116 	TEGRA_PIN_KB_COL5_PQ5,
1117 	TEGRA_PIN_KB_COL6_PQ6,
1118 	TEGRA_PIN_KB_COL7_PQ7,
1119 	TEGRA_PIN_KB_ROW8_PS0,
1120 	TEGRA_PIN_KB_ROW9_PS1,
1121 	TEGRA_PIN_KB_ROW10_PS2,
1122 	TEGRA_PIN_SYS_CLK_REQ_PZ5,
1123 	TEGRA_PIN_CORE_PWR_REQ,
1124 	TEGRA_PIN_CPU_PWR_REQ,
1125 	TEGRA_PIN_RESET_OUT_N,
1126 };
1127 
1128 static const unsigned drive_at1_pins[] = {
1129 	TEGRA_PIN_GMI_AD8_PH0,
1130 	TEGRA_PIN_GMI_AD9_PH1,
1131 	TEGRA_PIN_GMI_AD10_PH2,
1132 	TEGRA_PIN_GMI_AD11_PH3,
1133 	TEGRA_PIN_GMI_AD12_PH4,
1134 	TEGRA_PIN_GMI_AD13_PH5,
1135 	TEGRA_PIN_GMI_AD14_PH6,
1136 	TEGRA_PIN_GMI_AD15_PH7,
1137 	TEGRA_PIN_GMI_IORDY_PI5,
1138 	TEGRA_PIN_GMI_CS7_N_PI6,
1139 };
1140 
1141 static const unsigned drive_at2_pins[] = {
1142 	TEGRA_PIN_GMI_AD0_PG0,
1143 	TEGRA_PIN_GMI_AD1_PG1,
1144 	TEGRA_PIN_GMI_AD2_PG2,
1145 	TEGRA_PIN_GMI_AD3_PG3,
1146 	TEGRA_PIN_GMI_AD4_PG4,
1147 	TEGRA_PIN_GMI_AD5_PG5,
1148 	TEGRA_PIN_GMI_AD6_PG6,
1149 	TEGRA_PIN_GMI_AD7_PG7,
1150 	TEGRA_PIN_GMI_WR_N_PI0,
1151 	TEGRA_PIN_GMI_OE_N_PI1,
1152 	TEGRA_PIN_GMI_CS6_N_PI3,
1153 	TEGRA_PIN_GMI_RST_N_PI4,
1154 	TEGRA_PIN_GMI_WAIT_PI7,
1155 	TEGRA_PIN_GMI_DQS_P_PJ3,
1156 	TEGRA_PIN_GMI_ADV_N_PK0,
1157 	TEGRA_PIN_GMI_CLK_PK1,
1158 	TEGRA_PIN_GMI_CS4_N_PK2,
1159 	TEGRA_PIN_GMI_CS2_N_PK3,
1160 	TEGRA_PIN_GMI_CS3_N_PK4,
1161 };
1162 
1163 static const unsigned drive_at3_pins[] = {
1164 	TEGRA_PIN_GMI_WP_N_PC7,
1165 	TEGRA_PIN_GMI_CS0_N_PJ0,
1166 };
1167 
1168 static const unsigned drive_at4_pins[] = {
1169 	TEGRA_PIN_GMI_A17_PB0,
1170 	TEGRA_PIN_GMI_A18_PB1,
1171 	TEGRA_PIN_GMI_CS1_N_PJ2,
1172 	TEGRA_PIN_GMI_A16_PJ7,
1173 	TEGRA_PIN_GMI_A19_PK7,
1174 };
1175 
1176 static const unsigned drive_at5_pins[] = {
1177 	TEGRA_PIN_GEN2_I2C_SCL_PT5,
1178 	TEGRA_PIN_GEN2_I2C_SDA_PT6,
1179 };
1180 
1181 static const unsigned drive_cdev1_pins[] = {
1182 	TEGRA_PIN_CLK1_OUT_PW4,
1183 	TEGRA_PIN_CLK1_REQ_PEE2,
1184 };
1185 
1186 static const unsigned drive_cdev2_pins[] = {
1187 	TEGRA_PIN_CLK2_OUT_PW5,
1188 	TEGRA_PIN_CLK2_REQ_PCC5,
1189 	TEGRA_PIN_SDMMC1_WP_N_PV3,
1190 };
1191 
1192 static const unsigned drive_dap1_pins[] = {
1193 	TEGRA_PIN_DAP1_FS_PN0,
1194 	TEGRA_PIN_DAP1_DIN_PN1,
1195 	TEGRA_PIN_DAP1_DOUT_PN2,
1196 	TEGRA_PIN_DAP1_SCLK_PN3,
1197 };
1198 
1199 static const unsigned drive_dap2_pins[] = {
1200 	TEGRA_PIN_DAP2_FS_PA2,
1201 	TEGRA_PIN_DAP2_SCLK_PA3,
1202 	TEGRA_PIN_DAP2_DIN_PA4,
1203 	TEGRA_PIN_DAP2_DOUT_PA5,
1204 };
1205 
1206 static const unsigned drive_dap3_pins[] = {
1207 	TEGRA_PIN_DAP3_FS_PP0,
1208 	TEGRA_PIN_DAP3_DIN_PP1,
1209 	TEGRA_PIN_DAP3_DOUT_PP2,
1210 	TEGRA_PIN_DAP3_SCLK_PP3,
1211 };
1212 
1213 static const unsigned drive_dap4_pins[] = {
1214 	TEGRA_PIN_DAP4_FS_PP4,
1215 	TEGRA_PIN_DAP4_DIN_PP5,
1216 	TEGRA_PIN_DAP4_DOUT_PP6,
1217 	TEGRA_PIN_DAP4_SCLK_PP7,
1218 };
1219 
1220 static const unsigned drive_dbg_pins[] = {
1221 	TEGRA_PIN_GEN1_I2C_SCL_PC4,
1222 	TEGRA_PIN_GEN1_I2C_SDA_PC5,
1223 	TEGRA_PIN_PU0,
1224 	TEGRA_PIN_PU1,
1225 	TEGRA_PIN_PU2,
1226 	TEGRA_PIN_PU3,
1227 	TEGRA_PIN_PU4,
1228 	TEGRA_PIN_PU5,
1229 	TEGRA_PIN_PU6,
1230 };
1231 
1232 static const unsigned drive_sdio3_pins[] = {
1233 	TEGRA_PIN_SDMMC3_CLK_PA6,
1234 	TEGRA_PIN_SDMMC3_CMD_PA7,
1235 	TEGRA_PIN_SDMMC3_DAT3_PB4,
1236 	TEGRA_PIN_SDMMC3_DAT2_PB5,
1237 	TEGRA_PIN_SDMMC3_DAT1_PB6,
1238 	TEGRA_PIN_SDMMC3_DAT0_PB7,
1239 	TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1240 	TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1241 };
1242 
1243 static const unsigned drive_spi_pins[] = {
1244 	TEGRA_PIN_DVFS_PWM_PX0,
1245 	TEGRA_PIN_GPIO_X1_AUD_PX1,
1246 	TEGRA_PIN_DVFS_CLK_PX2,
1247 	TEGRA_PIN_GPIO_X3_AUD_PX3,
1248 	TEGRA_PIN_GPIO_X4_AUD_PX4,
1249 	TEGRA_PIN_GPIO_X5_AUD_PX5,
1250 	TEGRA_PIN_GPIO_X6_AUD_PX6,
1251 	TEGRA_PIN_GPIO_X7_AUD_PX7,
1252 	TEGRA_PIN_GPIO_W2_AUD_PW2,
1253 	TEGRA_PIN_GPIO_W3_AUD_PW3,
1254 };
1255 
1256 static const unsigned drive_uaa_pins[] = {
1257 	TEGRA_PIN_ULPI_DATA0_PO1,
1258 	TEGRA_PIN_ULPI_DATA1_PO2,
1259 	TEGRA_PIN_ULPI_DATA2_PO3,
1260 	TEGRA_PIN_ULPI_DATA3_PO4,
1261 };
1262 
1263 static const unsigned drive_uab_pins[] = {
1264 	TEGRA_PIN_ULPI_DATA7_PO0,
1265 	TEGRA_PIN_ULPI_DATA4_PO5,
1266 	TEGRA_PIN_ULPI_DATA5_PO6,
1267 	TEGRA_PIN_ULPI_DATA6_PO7,
1268 	TEGRA_PIN_PV0,
1269 	TEGRA_PIN_PV1,
1270 };
1271 
1272 static const unsigned drive_uart2_pins[] = {
1273 	TEGRA_PIN_UART2_TXD_PC2,
1274 	TEGRA_PIN_UART2_RXD_PC3,
1275 	TEGRA_PIN_UART2_CTS_N_PJ5,
1276 	TEGRA_PIN_UART2_RTS_N_PJ6,
1277 };
1278 
1279 static const unsigned drive_uart3_pins[] = {
1280 	TEGRA_PIN_UART3_CTS_N_PA1,
1281 	TEGRA_PIN_UART3_RTS_N_PC0,
1282 	TEGRA_PIN_UART3_TXD_PW6,
1283 	TEGRA_PIN_UART3_RXD_PW7,
1284 };
1285 
1286 static const unsigned drive_sdio1_pins[] = {
1287 	TEGRA_PIN_SDMMC1_DAT3_PY4,
1288 	TEGRA_PIN_SDMMC1_DAT2_PY5,
1289 	TEGRA_PIN_SDMMC1_DAT1_PY6,
1290 	TEGRA_PIN_SDMMC1_DAT0_PY7,
1291 	TEGRA_PIN_SDMMC1_CLK_PZ0,
1292 	TEGRA_PIN_SDMMC1_CMD_PZ1,
1293 };
1294 
1295 static const unsigned drive_ddc_pins[] = {
1296 	TEGRA_PIN_DDC_SCL_PV4,
1297 	TEGRA_PIN_DDC_SDA_PV5,
1298 };
1299 
1300 static const unsigned drive_gma_pins[] = {
1301 	TEGRA_PIN_SDMMC4_CLK_PCC4,
1302 	TEGRA_PIN_SDMMC4_CMD_PT7,
1303 	TEGRA_PIN_SDMMC4_DAT0_PAA0,
1304 	TEGRA_PIN_SDMMC4_DAT1_PAA1,
1305 	TEGRA_PIN_SDMMC4_DAT2_PAA2,
1306 	TEGRA_PIN_SDMMC4_DAT3_PAA3,
1307 	TEGRA_PIN_SDMMC4_DAT4_PAA4,
1308 	TEGRA_PIN_SDMMC4_DAT5_PAA5,
1309 	TEGRA_PIN_SDMMC4_DAT6_PAA6,
1310 	TEGRA_PIN_SDMMC4_DAT7_PAA7,
1311 };
1312 
1313 static const unsigned drive_gme_pins[] = {
1314 	TEGRA_PIN_PBB0,
1315 	TEGRA_PIN_CAM_I2C_SCL_PBB1,
1316 	TEGRA_PIN_CAM_I2C_SDA_PBB2,
1317 	TEGRA_PIN_PBB3,
1318 	TEGRA_PIN_PCC2,
1319 };
1320 
1321 static const unsigned drive_gmf_pins[] = {
1322 	TEGRA_PIN_PBB4,
1323 	TEGRA_PIN_PBB5,
1324 	TEGRA_PIN_PBB6,
1325 	TEGRA_PIN_PBB7,
1326 };
1327 
1328 static const unsigned drive_gmg_pins[] = {
1329 	TEGRA_PIN_CAM_MCLK_PCC0,
1330 };
1331 
1332 static const unsigned drive_gmh_pins[] = {
1333 	TEGRA_PIN_PCC1,
1334 };
1335 
1336 static const unsigned drive_owr_pins[] = {
1337 	TEGRA_PIN_SDMMC3_CD_N_PV2,
1338 };
1339 
1340 static const unsigned drive_uda_pins[] = {
1341 	TEGRA_PIN_ULPI_CLK_PY0,
1342 	TEGRA_PIN_ULPI_DIR_PY1,
1343 	TEGRA_PIN_ULPI_NXT_PY2,
1344 	TEGRA_PIN_ULPI_STP_PY3,
1345 };
1346 
1347 static const unsigned drive_dev3_pins[] = {
1348 };
1349 
1350 static const unsigned drive_cec_pins[] = {
1351 };
1352 
1353 static const unsigned drive_at6_pins[] = {
1354 };
1355 
1356 static const unsigned drive_dap5_pins[] = {
1357 };
1358 
1359 static const unsigned drive_usb_vbus_en_pins[] = {
1360 };
1361 
1362 static const unsigned drive_ao3_pins[] = {
1363 };
1364 
1365 static const unsigned drive_hv0_pins[] = {
1366 };
1367 
1368 static const unsigned drive_sdio4_pins[] = {
1369 };
1370 
1371 static const unsigned drive_ao0_pins[] = {
1372 };
1373 
1374 enum tegra_mux {
1375 	TEGRA_MUX_BLINK,
1376 	TEGRA_MUX_CEC,
1377 	TEGRA_MUX_CLDVFS,
1378 	TEGRA_MUX_CLK,
1379 	TEGRA_MUX_CLK12,
1380 	TEGRA_MUX_CPU,
1381 	TEGRA_MUX_DAP,
1382 	TEGRA_MUX_DAP1,
1383 	TEGRA_MUX_DAP2,
1384 	TEGRA_MUX_DEV3,
1385 	TEGRA_MUX_DISPLAYA,
1386 	TEGRA_MUX_DISPLAYA_ALT,
1387 	TEGRA_MUX_DISPLAYB,
1388 	TEGRA_MUX_DTV,
1389 	TEGRA_MUX_EMC_DLL,
1390 	TEGRA_MUX_EXTPERIPH1,
1391 	TEGRA_MUX_EXTPERIPH2,
1392 	TEGRA_MUX_EXTPERIPH3,
1393 	TEGRA_MUX_GMI,
1394 	TEGRA_MUX_GMI_ALT,
1395 	TEGRA_MUX_HDA,
1396 	TEGRA_MUX_HSI,
1397 	TEGRA_MUX_I2C1,
1398 	TEGRA_MUX_I2C2,
1399 	TEGRA_MUX_I2C3,
1400 	TEGRA_MUX_I2C4,
1401 	TEGRA_MUX_I2CPWR,
1402 	TEGRA_MUX_I2S0,
1403 	TEGRA_MUX_I2S1,
1404 	TEGRA_MUX_I2S2,
1405 	TEGRA_MUX_I2S3,
1406 	TEGRA_MUX_I2S4,
1407 	TEGRA_MUX_IRDA,
1408 	TEGRA_MUX_KBC,
1409 	TEGRA_MUX_NAND,
1410 	TEGRA_MUX_NAND_ALT,
1411 	TEGRA_MUX_OWR,
1412 	TEGRA_MUX_PMI,
1413 	TEGRA_MUX_PWM0,
1414 	TEGRA_MUX_PWM1,
1415 	TEGRA_MUX_PWM2,
1416 	TEGRA_MUX_PWM3,
1417 	TEGRA_MUX_PWRON,
1418 	TEGRA_MUX_RESET_OUT_N,
1419 	TEGRA_MUX_RSVD1,
1420 	TEGRA_MUX_RSVD2,
1421 	TEGRA_MUX_RSVD3,
1422 	TEGRA_MUX_RSVD4,
1423 	TEGRA_MUX_RTCK,
1424 	TEGRA_MUX_SDMMC1,
1425 	TEGRA_MUX_SDMMC2,
1426 	TEGRA_MUX_SDMMC3,
1427 	TEGRA_MUX_SDMMC4,
1428 	TEGRA_MUX_SOC,
1429 	TEGRA_MUX_SPDIF,
1430 	TEGRA_MUX_SPI1,
1431 	TEGRA_MUX_SPI2,
1432 	TEGRA_MUX_SPI3,
1433 	TEGRA_MUX_SPI4,
1434 	TEGRA_MUX_SPI5,
1435 	TEGRA_MUX_SPI6,
1436 	TEGRA_MUX_SYSCLK,
1437 	TEGRA_MUX_TRACE,
1438 	TEGRA_MUX_UARTA,
1439 	TEGRA_MUX_UARTB,
1440 	TEGRA_MUX_UARTC,
1441 	TEGRA_MUX_UARTD,
1442 	TEGRA_MUX_ULPI,
1443 	TEGRA_MUX_USB,
1444 	TEGRA_MUX_VGP1,
1445 	TEGRA_MUX_VGP2,
1446 	TEGRA_MUX_VGP3,
1447 	TEGRA_MUX_VGP4,
1448 	TEGRA_MUX_VGP5,
1449 	TEGRA_MUX_VGP6,
1450 	TEGRA_MUX_VI,
1451 	TEGRA_MUX_VI_ALT1,
1452 	TEGRA_MUX_VI_ALT3,
1453 };
1454 
1455 #define FUNCTION(fname) #fname
1456 
1457 static const char * const tegra114_functions[] = {
1458 	FUNCTION(blink),
1459 	FUNCTION(cec),
1460 	FUNCTION(cldvfs),
1461 	FUNCTION(clk),
1462 	FUNCTION(clk12),
1463 	FUNCTION(cpu),
1464 	FUNCTION(dap),
1465 	FUNCTION(dap1),
1466 	FUNCTION(dap2),
1467 	FUNCTION(dev3),
1468 	FUNCTION(displaya),
1469 	FUNCTION(displaya_alt),
1470 	FUNCTION(displayb),
1471 	FUNCTION(dtv),
1472 	FUNCTION(emc_dll),
1473 	FUNCTION(extperiph1),
1474 	FUNCTION(extperiph2),
1475 	FUNCTION(extperiph3),
1476 	FUNCTION(gmi),
1477 	FUNCTION(gmi_alt),
1478 	FUNCTION(hda),
1479 	FUNCTION(hsi),
1480 	FUNCTION(i2c1),
1481 	FUNCTION(i2c2),
1482 	FUNCTION(i2c3),
1483 	FUNCTION(i2c4),
1484 	FUNCTION(i2cpwr),
1485 	FUNCTION(i2s0),
1486 	FUNCTION(i2s1),
1487 	FUNCTION(i2s2),
1488 	FUNCTION(i2s3),
1489 	FUNCTION(i2s4),
1490 	FUNCTION(irda),
1491 	FUNCTION(kbc),
1492 	FUNCTION(nand),
1493 	FUNCTION(nand_alt),
1494 	FUNCTION(owr),
1495 	FUNCTION(pmi),
1496 	FUNCTION(pwm0),
1497 	FUNCTION(pwm1),
1498 	FUNCTION(pwm2),
1499 	FUNCTION(pwm3),
1500 	FUNCTION(pwron),
1501 	FUNCTION(reset_out_n),
1502 	FUNCTION(rsvd1),
1503 	FUNCTION(rsvd2),
1504 	FUNCTION(rsvd3),
1505 	FUNCTION(rsvd4),
1506 	FUNCTION(rtck),
1507 	FUNCTION(sdmmc1),
1508 	FUNCTION(sdmmc2),
1509 	FUNCTION(sdmmc3),
1510 	FUNCTION(sdmmc4),
1511 	FUNCTION(soc),
1512 	FUNCTION(spdif),
1513 	FUNCTION(spi1),
1514 	FUNCTION(spi2),
1515 	FUNCTION(spi3),
1516 	FUNCTION(spi4),
1517 	FUNCTION(spi5),
1518 	FUNCTION(spi6),
1519 	FUNCTION(sysclk),
1520 	FUNCTION(trace),
1521 	FUNCTION(uarta),
1522 	FUNCTION(uartb),
1523 	FUNCTION(uartc),
1524 	FUNCTION(uartd),
1525 	FUNCTION(ulpi),
1526 	FUNCTION(usb),
1527 	FUNCTION(vgp1),
1528 	FUNCTION(vgp2),
1529 	FUNCTION(vgp3),
1530 	FUNCTION(vgp4),
1531 	FUNCTION(vgp5),
1532 	FUNCTION(vgp6),
1533 	FUNCTION(vi),
1534 	FUNCTION(vi_alt1),
1535 	FUNCTION(vi_alt3),
1536 };
1537 
1538 #define DRV_PINGROUP_REG_A		0x868	/* bank 0 */
1539 #define PINGROUP_REG_A			0x3000	/* bank 1 */
1540 
1541 #define DRV_PINGROUP_REG(r)		((r) - DRV_PINGROUP_REG_A)
1542 #define PINGROUP_REG(r)			((r) - PINGROUP_REG_A)
1543 
1544 #define PINGROUP_BIT_Y(b)		(b)
1545 #define PINGROUP_BIT_N(b)		(-1)
1546 
1547 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel)		\
1548 	{								\
1549 		.name = #pg_name,					\
1550 		.pins = pg_name##_pins,					\
1551 		.npins = ARRAY_SIZE(pg_name##_pins),			\
1552 		.funcs = {						\
1553 			TEGRA_MUX_##f0,					\
1554 			TEGRA_MUX_##f1,					\
1555 			TEGRA_MUX_##f2,					\
1556 			TEGRA_MUX_##f3,					\
1557 		},							\
1558 		.mux_reg = PINGROUP_REG(r),				\
1559 		.mux_bank = 1,						\
1560 		.mux_bit = 0,						\
1561 		.pupd_reg = PINGROUP_REG(r),				\
1562 		.pupd_bank = 1,						\
1563 		.pupd_bit = 2,						\
1564 		.tri_reg = PINGROUP_REG(r),				\
1565 		.tri_bank = 1,						\
1566 		.tri_bit = 4,						\
1567 		.einput_bit = 5,					\
1568 		.odrain_bit = PINGROUP_BIT_##od(6),			\
1569 		.lock_bit = 7,						\
1570 		.ioreset_bit = PINGROUP_BIT_##ior(8),			\
1571 		.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9),		\
1572 		.drv_reg = -1,						\
1573 		.parked_bitmask = 0,					\
1574 	}
1575 
1576 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b,	\
1577 		     drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w,		\
1578 		     slwf_b, slwf_w, drvtype)				\
1579 	{								\
1580 		.name = "drive_" #pg_name,				\
1581 		.pins = drive_##pg_name##_pins,				\
1582 		.npins = ARRAY_SIZE(drive_##pg_name##_pins),		\
1583 		.mux_reg = -1,						\
1584 		.pupd_reg = -1,						\
1585 		.tri_reg = -1,						\
1586 		.einput_bit = -1,					\
1587 		.odrain_bit = -1,					\
1588 		.lock_bit = -1,						\
1589 		.ioreset_bit = -1,					\
1590 		.rcv_sel_bit = -1,					\
1591 		.drv_reg = DRV_PINGROUP_REG(r),				\
1592 		.drv_bank = 0,						\
1593 		.hsm_bit = hsm_b,					\
1594 		.schmitt_bit = schmitt_b,				\
1595 		.lpmd_bit = lpmd_b,					\
1596 		.drvdn_bit = drvdn_b,					\
1597 		.drvdn_width = drvdn_w,					\
1598 		.drvup_bit = drvup_b,					\
1599 		.drvup_width = drvup_w,					\
1600 		.slwr_bit = slwr_b,					\
1601 		.slwr_width = slwr_w,					\
1602 		.slwf_bit = slwf_b,					\
1603 		.slwf_width = slwf_w,					\
1604 		.drvtype_bit = PINGROUP_BIT_##drvtype(6),		\
1605 		.parked_bitmask = 0,					\
1606 	}
1607 
1608 static const struct tegra_pingroup tegra114_groups[] = {
1609 	/*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
1610 	PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
1611 	PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        0x3004, N,   N,  N),
1612 	PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        0x3008, N,   N,  N),
1613 	PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        0x300c, N,   N,  N),
1614 	PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        0x3010, N,   N,  N),
1615 	PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        0x3014, N,   N,  N),
1616 	PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        0x3018, N,   N,  N),
1617 	PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        0x301c, N,   N,  N),
1618 	PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        0x3020, N,   N,  N),
1619 	PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        0x3024, N,   N,  N),
1620 	PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        0x3028, N,   N,  N),
1621 	PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        0x302c, N,   N,  N),
1622 	PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3030, N,   N,  N),
1623 	PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3034, N,   N,  N),
1624 	PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3038, N,   N,  N),
1625 	PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x303c, N,   N,  N),
1626 	PINGROUP(pv0,                    USB,        RSVD2,      RSVD3,        RSVD4,       0x3040, N,   N,  N),
1627 	PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3044, N,   N,  N),
1628 	PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       0x3048, N,   N,  N),
1629 	PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       0x304c, N,   N,  N),
1630 	PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       0x3050, N,   N,  N),
1631 	PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       0x3054, N,   N,  N),
1632 	PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       0x3058, N,   N,  N),
1633 	PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       0x305c, N,   N,  N),
1634 	PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       0x3068, N,   N,  N),
1635 	PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       0x306c, N,   N,  N),
1636 	PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3110, N,   N,  Y),
1637 	PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3114, N,   N,  Y),
1638 	PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3118, N,   N,  Y),
1639 	PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3164, N,   N,  N),
1640 	PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3168, N,   N,  N),
1641 	PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      RSVD3,        SPI4,        0x316c, N,   N,  N),
1642 	PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      RSVD3,        SPI4,        0x3170, N,   N,  N),
1643 	PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      RSVD3,        SPI4,        0x3174, N,   N,  N),
1644 	PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      RSVD3,        SPI4,        0x3178, N,   N,  N),
1645 	PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          SPI4,        0x317c, N,   N,  N),
1646 	PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          DISPLAYA,    0x3180, N,   N,  N),
1647 	PINGROUP(pu0,                    OWR,        UARTA,      RSVD3,        RSVD4,       0x3184, N,   N,  N),
1648 	PINGROUP(pu1,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       0x3188, N,   N,  N),
1649 	PINGROUP(pu2,                    RSVD1,      UARTA,      RSVD3,        RSVD4,       0x318c, N,   N,  N),
1650 	PINGROUP(pu3,                    PWM0,       UARTA,      DISPLAYA,     DISPLAYB,    0x3190, N,   N,  N),
1651 	PINGROUP(pu4,                    PWM1,       UARTA,      DISPLAYA,     DISPLAYB,    0x3194, N,   N,  N),
1652 	PINGROUP(pu5,                    PWM2,       UARTA,      DISPLAYA,     DISPLAYB,    0x3198, N,   N,  N),
1653 	PINGROUP(pu6,                    PWM3,       UARTA,      USB,          DISPLAYB,    0x319c, N,   N,  N),
1654 	PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a0, Y,   N,  N),
1655 	PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a4, Y,   N,  N),
1656 	PINGROUP(dap4_fs_pp4,            I2S3,       RSVD2,      DTV,          RSVD4,       0x31a8, N,   N,  N),
1657 	PINGROUP(dap4_din_pp5,           I2S3,       RSVD2,      RSVD3,        RSVD4,       0x31ac, N,   N,  N),
1658 	PINGROUP(dap4_dout_pp6,          I2S3,       RSVD2,      DTV,          RSVD4,       0x31b0, N,   N,  N),
1659 	PINGROUP(dap4_sclk_pp7,          I2S3,       RSVD2,      RSVD3,        RSVD4,       0x31b4, N,   N,  N),
1660 	PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       0x31b8, N,   N,  N),
1661 	PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       0x31bc, N,   N,  N),
1662 	PINGROUP(gmi_wp_n_pc7,           RSVD1,      NAND,       GMI,          GMI_ALT,     0x31c0, N,   N,  N),
1663 	PINGROUP(gmi_iordy_pi5,          SDMMC2,     RSVD2,      GMI,          TRACE,       0x31c4, N,   N,  N),
1664 	PINGROUP(gmi_wait_pi7,           SPI4,       NAND,       GMI,          DTV,         0x31c8, N,   N,  N),
1665 	PINGROUP(gmi_adv_n_pk0,          RSVD1,      NAND,       GMI,          TRACE,       0x31cc, N,   N,  N),
1666 	PINGROUP(gmi_clk_pk1,            SDMMC2,     NAND,       GMI,          TRACE,       0x31d0, N,   N,  N),
1667 	PINGROUP(gmi_cs0_n_pj0,          RSVD1,      NAND,       GMI,          USB,         0x31d4, N,   N,  N),
1668 	PINGROUP(gmi_cs1_n_pj2,          RSVD1,      NAND,       GMI,          SOC,         0x31d8, N,   N,  N),
1669 	PINGROUP(gmi_cs2_n_pk3,          SDMMC2,     NAND,       GMI,          TRACE,       0x31dc, N,   N,  N),
1670 	PINGROUP(gmi_cs3_n_pk4,          SDMMC2,     NAND,       GMI,          GMI_ALT,     0x31e0, N,   N,  N),
1671 	PINGROUP(gmi_cs4_n_pk2,          USB,        NAND,       GMI,          TRACE,       0x31e4, N,   N,  N),
1672 	PINGROUP(gmi_cs6_n_pi3,          NAND,       NAND_ALT,   GMI,          SPI4,        0x31e8, N,   N,  N),
1673 	PINGROUP(gmi_cs7_n_pi6,          NAND,       NAND_ALT,   GMI,          SDMMC2,      0x31ec, N,   N,  N),
1674 	PINGROUP(gmi_ad0_pg0,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f0, N,   N,  N),
1675 	PINGROUP(gmi_ad1_pg1,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f4, N,   N,  N),
1676 	PINGROUP(gmi_ad2_pg2,            RSVD1,      NAND,       GMI,          RSVD4,       0x31f8, N,   N,  N),
1677 	PINGROUP(gmi_ad3_pg3,            RSVD1,      NAND,       GMI,          RSVD4,       0x31fc, N,   N,  N),
1678 	PINGROUP(gmi_ad4_pg4,            RSVD1,      NAND,       GMI,          RSVD4,       0x3200, N,   N,  N),
1679 	PINGROUP(gmi_ad5_pg5,            RSVD1,      NAND,       GMI,          SPI4,        0x3204, N,   N,  N),
1680 	PINGROUP(gmi_ad6_pg6,            RSVD1,      NAND,       GMI,          SPI4,        0x3208, N,   N,  N),
1681 	PINGROUP(gmi_ad7_pg7,            RSVD1,      NAND,       GMI,          SPI4,        0x320c, N,   N,  N),
1682 	PINGROUP(gmi_ad8_ph0,            PWM0,       NAND,       GMI,          DTV,         0x3210, N,   N,  N),
1683 	PINGROUP(gmi_ad9_ph1,            PWM1,       NAND,       GMI,          CLDVFS,      0x3214, N,   N,  N),
1684 	PINGROUP(gmi_ad10_ph2,           PWM2,       NAND,       GMI,          CLDVFS,      0x3218, N,   N,  N),
1685 	PINGROUP(gmi_ad11_ph3,           PWM3,       NAND,       GMI,          USB,         0x321c, N,   N,  N),
1686 	PINGROUP(gmi_ad12_ph4,           SDMMC2,     NAND,       GMI,          RSVD4,       0x3220, N,   N,  N),
1687 	PINGROUP(gmi_ad13_ph5,           SDMMC2,     NAND,       GMI,          RSVD4,       0x3224, N,   N,  N),
1688 	PINGROUP(gmi_ad14_ph6,           SDMMC2,     NAND,       GMI,          DTV,         0x3228, N,   N,  N),
1689 	PINGROUP(gmi_ad15_ph7,           SDMMC2,     NAND,       GMI,          DTV,         0x322c, N,   N,  N),
1690 	PINGROUP(gmi_a16_pj7,            UARTD,      TRACE,      GMI,          GMI_ALT,     0x3230, N,   N,  N),
1691 	PINGROUP(gmi_a17_pb0,            UARTD,      RSVD2,      GMI,          TRACE,       0x3234, N,   N,  N),
1692 	PINGROUP(gmi_a18_pb1,            UARTD,      RSVD2,      GMI,          TRACE,       0x3238, N,   N,  N),
1693 	PINGROUP(gmi_a19_pk7,            UARTD,      SPI4,       GMI,          TRACE,       0x323c, N,   N,  N),
1694 	PINGROUP(gmi_wr_n_pi0,           RSVD1,      NAND,       GMI,          SPI4,        0x3240, N,   N,  N),
1695 	PINGROUP(gmi_oe_n_pi1,           RSVD1,      NAND,       GMI,          SOC,         0x3244, N,   N,  N),
1696 	PINGROUP(gmi_dqs_p_pj3,          SDMMC2,     NAND,       GMI,          TRACE,       0x3248, N,   N,  N),
1697 	PINGROUP(gmi_rst_n_pi4,          NAND,       NAND_ALT,   GMI,          RSVD4,       0x324c, N,   N,  N),
1698 	PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3250, Y,   N,  N),
1699 	PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3254, Y,   N,  N),
1700 	PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       0x3258, N,   Y,  N),
1701 	PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       0x325c, N,   Y,  N),
1702 	PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3260, N,   Y,  N),
1703 	PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3264, N,   Y,  N),
1704 	PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3268, N,   Y,  N),
1705 	PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x326c, N,   Y,  N),
1706 	PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3270, N,   Y,  N),
1707 	PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3274, N,   Y,  N),
1708 	PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3278, N,   Y,  N),
1709 	PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       0x327c, N,   Y,  N),
1710 	PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      RSVD4,       0x3284, N,   N,  N),
1711 	PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x3288, N,   N,  N),
1712 	PINGROUP(pbb0,                   I2S4,       VI,         VI_ALT1,      VI_ALT3,     0x328c, N,   N,  N),
1713 	PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        RSVD4,       0x3290, Y,   N,  N),
1714 	PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        RSVD4,       0x3294, Y,   N,  N),
1715 	PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     RSVD4,       0x3298, N,   N,  N),
1716 	PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     RSVD4,       0x329c, N,   N,  N),
1717 	PINGROUP(pbb5,                   VGP5,       DISPLAYA,   DISPLAYB,     RSVD4,       0x32a0, N,   N,  N),
1718 	PINGROUP(pbb6,                   VGP6,       DISPLAYA,   DISPLAYB,     RSVD4,       0x32a4, N,   N,  N),
1719 	PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x32a8, N,   N,  N),
1720 	PINGROUP(pcc2,                   I2S4,       RSVD2,      RSVD3,        RSVD4,       0x32ac, N,   N,  N),
1721 	PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       0x32b0, N,   N,  N),
1722 	PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b4, Y,   N,  N),
1723 	PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b8, Y,   N,  N),
1724 	PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32bc, N,   N,  N),
1725 	PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c0, N,   N,  N),
1726 	PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c4, N,   N,  N),
1727 	PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32c8, N,   N,  N),
1728 	PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    0x32cc, N,   N,  N),
1729 	PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   SPI2,         DISPLAYB,    0x32d0, N,   N,  N),
1730 	PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    0x32d4, N,   N,  N),
1731 	PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32d8, N,   N,  N),
1732 	PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32dc, N,   N,  N),
1733 	PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       0x32e0, N,   N,  N),
1734 	PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       0x32e4, N,   N,  N),
1735 	PINGROUP(kb_col0_pq0,            KBC,        USB,        SPI2,         EMC_DLL,     0x32fc, N,   N,  N),
1736 	PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         EMC_DLL,     0x3300, N,   N,  N),
1737 	PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3304, N,   N,  N),
1738 	PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       0x3308, N,   N,  N),
1739 	PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       0x330c, N,   N,  N),
1740 	PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC1,       RSVD4,       0x3310, N,   N,  N),
1741 	PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3314, N,   N,  N),
1742 	PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3318, N,   N,  N),
1743 	PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       0x331c, N,   N,  N),
1744 	PINGROUP(sys_clk_req_pz5,        SYSCLK,     RSVD2,      RSVD3,        RSVD4,       0x3320, N,   N,  N),
1745 	PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       0x3324, N,   N,  N),
1746 	PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       0x3328, N,   N,  N),
1747 	PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       0x332c, N,   N,  N),
1748 	PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       0x3330, N,   N,  N),
1749 	PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       0x3334, N,   N,  Y),
1750 	PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       0x3338, N,   N,  N),
1751 	PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       0x333c, N,   N,  N),
1752 	PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          RSVD4,       0x3340, N,   N,  N),
1753 	PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       0x3344, N,   N,  N),
1754 	PINGROUP(clk1_req_pee2,          DAP,        DAP1,       RSVD3,        RSVD4,       0x3348, N,   N,  N),
1755 	PINGROUP(clk1_out_pw4,           EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       0x334c, N,   N,  N),
1756 	PINGROUP(spdif_in_pk6,           SPDIF,      USB,        RSVD3,        RSVD4,       0x3350, N,   N,  N),
1757 	PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        RSVD4,       0x3354, N,   N,  N),
1758 	PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        RSVD3,        RSVD4,       0x3358, N,   N,  N),
1759 	PINGROUP(dap2_din_pa4,           I2S1,       HDA,        RSVD3,        RSVD4,       0x335c, N,   N,  N),
1760 	PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        RSVD3,        RSVD4,       0x3360, N,   N,  N),
1761 	PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        RSVD3,        RSVD4,       0x3364, N,   N,  N),
1762 	PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       0x3368, N,   N,  N),
1763 	PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      RSVD3,        RSVD4,       0x336c, N,   N,  N),
1764 	PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       RSVD3,        RSVD4,       0x3370, N,   N,  N),
1765 	PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     RSVD3,        RSVD4,       0x3374, N,   N,  N),
1766 	PINGROUP(gpio_x4_aud_px4,        RSVD1,      SPI1,       SPI2,         DAP2,        0x3378, N,   N,  N),
1767 	PINGROUP(gpio_x5_aud_px5,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x337c, N,   N,  N),
1768 	PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         RSVD4,       0x3380, N,   N,  N),
1769 	PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x3384, N,   N,  N),
1770 	PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3390, N,   N,  N),
1771 	PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        0x3394, N,   N,  N),
1772 	PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3398, N,   N,  N),
1773 	PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        0x339c, N,   N,  N),
1774 	PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        0x33a0, N,   N,  N),
1775 	PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        0x33a4, N,   N,  N),
1776 	PINGROUP(hdmi_cec_pee3,          CEC,        SDMMC3,     RSVD3,        SOC,         0x33e0, Y,   N,  N),
1777 	PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       0x33e4, N,   N,  N),
1778 	PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       0x33e8, N,   N,  N),
1779 	PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        0x33ec, N,   N,  N),
1780 	PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        0x33f0, N,   N,  N),
1781 	PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f4, Y,   N,  N),
1782 	PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f8, Y,   N,  N),
1783 	PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x33fc, N,   N,  N),
1784 	PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x3400, N,   N,  N),
1785 	PINGROUP(gmi_clk_lb,             SDMMC2,     NAND,       GMI,          RSVD4,       0x3404, N,   N,  N),
1786 	PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, 0x3408, N,   N,  N),
1787 
1788 	/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1789 	DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1790 	DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1791 	DRV_PINGROUP(at1,         0x870,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1792 	DRV_PINGROUP(at2,         0x874,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1793 	DRV_PINGROUP(at3,         0x878,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1794 	DRV_PINGROUP(at4,         0x87c,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
1795 	DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1796 	DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1797 	DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1798 	DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1799 	DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1800 	DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1801 	DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1802 	DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1803 	DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1804 	DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1805 	DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1806 	DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1807 	DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1808 	DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1809 	DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
1810 	DRV_PINGROUP(ddc,         0x8fc,  2,  3, -1,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1811 	DRV_PINGROUP(gma,         0x900,  2,  3, -1,  14,  5,  20,  5,  28,  2,  30,  2,  N),
1812 	DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1813 	DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1814 	DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1815 	DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
1816 	DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1817 	DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1818 	DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1819 	DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1820 	DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  Y),
1821 	DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1822 	DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1823 	DRV_PINGROUP(ao3,         0x9a0,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1824 	DRV_PINGROUP(hv0,         0x9a4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
1825 	DRV_PINGROUP(sdio4,       0x9a8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1826 	DRV_PINGROUP(ao0,         0x9ac,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
1827 };
1828 
1829 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
1830 	.ngpios = NUM_GPIOS,
1831 	.gpio_compatible = "nvidia,tegra114-gpio",
1832 	.pins = tegra114_pins,
1833 	.npins = ARRAY_SIZE(tegra114_pins),
1834 	.functions = tegra114_functions,
1835 	.nfunctions = ARRAY_SIZE(tegra114_functions),
1836 	.groups = tegra114_groups,
1837 	.ngroups = ARRAY_SIZE(tegra114_groups),
1838 	.hsm_in_mux = false,
1839 	.schmitt_in_mux = false,
1840 	.drvtype_in_mux = false,
1841 };
1842 
tegra114_pinctrl_probe(struct platform_device * pdev)1843 static int tegra114_pinctrl_probe(struct platform_device *pdev)
1844 {
1845 	return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
1846 }
1847 
1848 static const struct of_device_id tegra114_pinctrl_of_match[] = {
1849 	{ .compatible = "nvidia,tegra114-pinmux", },
1850 	{ },
1851 };
1852 
1853 static struct platform_driver tegra114_pinctrl_driver = {
1854 	.driver = {
1855 		.name = "tegra114-pinctrl",
1856 		.of_match_table = tegra114_pinctrl_of_match,
1857 	},
1858 	.probe = tegra114_pinctrl_probe,
1859 };
1860 
tegra114_pinctrl_init(void)1861 static int __init tegra114_pinctrl_init(void)
1862 {
1863 	return platform_driver_register(&tegra114_pinctrl_driver);
1864 }
1865 arch_initcall(tegra114_pinctrl_init);
1866