Searched refs:g_ctl (Results 1 – 4 of 4) sorted by relevance
175 u8 g_ctl = 0; in horus3a_set_params() local205 g_ctl = 0x01; in horus3a_set_params()209 g_ctl = 0x02; in horus3a_set_params()213 g_ctl = 0x02; in horus3a_set_params()217 g_ctl = 0x03; in horus3a_set_params()221 g_ctl = 0x04; in horus3a_set_params()225 g_ctl = 0x04; in horus3a_set_params()229 g_ctl = 0x05; in horus3a_set_params()233 g_ctl = 0x02; in horus3a_set_params()237 g_ctl = 0x01; in horus3a_set_params()[all …]
29 clrsetbits_le32(&dwc3_reg->g_ctl, in dwc3_set_mode()54 setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); in dwc3_core_soft_reset()62 clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); in dwc3_core_soft_reset()82 reg = readl(&dwc3_reg->g_ctl); in dwc3_core_init()102 writel(reg, &dwc3_reg->g_ctl); in dwc3_core_init()
61 u32 g_ctl; member
150 uint32_t g_ctl; member514 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { in intel_hda_set_g_ctl()639 .offset = offsetof(IntelHDAState, g_ctl),1181 VMSTATE_UINT32(g_ctl, IntelHDAState),