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Searched refs:fq_mask (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/riscv/
H A Driscv-iommu.h52 uint32_t fq_mask; /* Fault/event queue index bit mask */ member
H A Driscv-iommu.c118 uint32_t head = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQH) & s->fq_mask; in riscv_iommu_fault()
119 uint32_t tail = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FQT) & s->fq_mask; in riscv_iommu_fault()
120 uint32_t next = (tail + 1) & s->fq_mask; in riscv_iommu_fault()
1734 s->fq_mask = (2ULL << get_field(base, RISCV_IOMMU_FQB_LOG2SZ)) - 1; in riscv_iommu_process_fq_control()
1736 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_FQH], ~s->fq_mask); in riscv_iommu_process_fq_control()