Searched refs:fpccr (Results 1 – 8 of 8) sorted by relevance
368 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in HELPER()369 bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); in HELPER()370 bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); in HELPER()371 bool splimviol = env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_MASK; in HELPER()374 bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); in HELPER()438 env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; in HELPER()995 uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; in v7m_update_fpccr()996 uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; in v7m_update_fpccr()997 uint32_t *fpccr = &env->v7m.fpccr[is_secure]; in v7m_update_fpccr() local1009 *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); in v7m_update_fpccr()[all …]
133 aspen = load_cpu_field(v7m.fpccr[M_REG_S]); in trans_VSCCLRM()296 aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); in gen_branch_fpInactive()
161 tmp = load_cpu_field(v7m.fpccr[M_REG_S]); in gen_update_fp_context()167 store_cpu_field(tmp, v7m.fpccr[M_REG_S]); in gen_update_fp_context()
691 uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; in armv7m_nvic_set_pending_lazyfp()692 uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; in armv7m_nvic_set_pending_lazyfp() local709 escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); in armv7m_nvic_set_pending_lazyfp()712 escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); in armv7m_nvic_set_pending_lazyfp()1508 return cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()1516 uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; in nvic_readl()1527 value |= cpu->env.v7m.fpccr[M_REG_NS]; in nvic_readl()2083 fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; in nvic_writel()2109 cpu->env.v7m.fpccr[M_REG_NS] = value; in nvic_writel()2113 cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; in nvic_writel()
447 env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; in arm_cpu_reset_hold() 448 env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | in arm_cpu_reset_hold() 494 env->v7m.fpccr[M_REG_S] &= in arm_cpu_reset_hold()
485 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS),
566 uint32_t fpccr[M_REG_NUM_BANKS];565 uint32_t fpccr[M_REG_NUM_BANKS]; global() member
12911 FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) in arm_security_space_below_el3() 12916 if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && in arm_security_space_below_el3() 12928 bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; in arm_security_space_below_el3() 12929 if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {