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Searched refs:fj (Results 1 – 9 of 9) sorted by relevance

/openbmc/qemu/target/loongarch/tcg/
H A Dfpu_helper.c249 fd = float64_scalbn(fj, in helper_fscaleb_d()
336 fd = float64_log2(fj, status); in helper_flogb_d()
345 float32 f = fj; in helper_fclass_s()
364 float64 f = fj; in helper_fclass_d()
545 if (float64_is_any_nan(fj)) { in helper_ftintrm_l_d()
581 if (float64_is_any_nan(fj)) { in helper_ftintrm_w_d()
617 if (float64_is_any_nan(fj)) { in helper_ftintrp_l_d()
653 if (float64_is_any_nan(fj)) { in helper_ftintrp_w_d()
688 if (float64_is_any_nan(fj)) { in helper_ftintrz_l_d()
722 if (float64_is_any_nan(fj)) { in helper_ftintrz_w_d()
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H A Dvec_helper.c2484 static T do_flogb_## BIT(CPULoongArchState *env, T fj) \
2491 fp = float ## BIT ##_log2(fj, status); \
2519 static T do_fsqrt_## BIT(CPULoongArchState *env, T fj) \
2522 fd = float ## BIT ##_sqrt(fj, &env->fp_status); \
2531 static T do_frecip_## BIT(CPULoongArchState *env, T fj) \
2534 fd = float ## BIT ##_div(float ## BIT ##_one, fj, &env->fp_status); \
2543 static T do_frsqrt_## BIT(CPULoongArchState *env, T fj) \
2546 fp = float ## BIT ##_sqrt(fj, &env->fp_status); \
2773 static T2 do_ftint ## NAME(CPULoongArchState *env, T1 fj) \
2929 static T2 do_ffint_ ## NAME(CPULoongArchState *env, T1 fj) \
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/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_farith.c.inc21 TCGv src1 = get_fpr(ctx, a->fj);
36 TCGv src = get_fpr(ctx, a->fj);
52 TCGv src1 = get_fpr(ctx, a->fj);
68 TCGv src2 = get_fpr(ctx, a->fj);
86 TCGv src2 = get_fpr(ctx, a->fj);
103 TCGv src = get_fpr(ctx, a->fj);
121 TCGv src = get_fpr(ctx, a->fj);
138 TCGv src = get_fpr(ctx, a->fj);
156 TCGv src = get_fpr(ctx, a->fj);
H A Dtrans_fcmp.c.inc39 src1 = get_fpr(ctx, a->fj);
63 src1 = get_fpr(ctx, a->fj);
H A Dtrans_fmov.c.inc14 TCGv src1 = get_fpr(ctx, a->fj);
36 TCGv src = get_fpr(ctx, a->fj);
71 TCGv src = get_fpr(ctx, a->fj);
155 TCGv src = get_fpr(ctx, a->fj);
/openbmc/qemu/tests/tcg/loongarch64/
H A Dtest_fpcom.c4 void test_##N(float fj, float fk) \
11 : "f"(fj), "f"(fk) \
/openbmc/qemu/target/loongarch/
H A Dinsns.decode30 &ff fd fj
31 &fff fd fj fk
32 &ffff fd fj fk fa
33 &cff_fcond cd fj fk fcond
34 &fffc fd fj fk ca
36 &rf rd fj
39 &cf cd fj
79 @ff .... ........ ..... ..... fj:5 fd:5 &ff
80 @fff .... ........ ..... fk:5 fj:5 fd:5 &fff
85 @rf .... ........ ..... ..... fj:5 rd:5 &rf
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H A Ddisas.c217 output(ctx, mnemonic, "f%d, f%d", a->fd, a->fj); in output_ff()
222 output(ctx, mnemonic, "f%d, f%d, f%d", a->fd, a->fj, a->fk); in output_fff()
227 output(ctx, mnemonic, "f%d, f%d, f%d, f%d", a->fd, a->fj, a->fk, a->fa); in output_ffff()
232 output(ctx, mnemonic, "f%d, f%d, f%d, %d", a->fd, a->fj, a->fk, a->ca); in output_fffc()
242 output(ctx, mnemonic, "r%d, f%d", a->rd, a->fj); in output_rf()
259 output(ctx, mnemonic, "fcc%d, f%d", a->cd, a->fj); in output_cf()
687 a->fj, a->fk); \ in INSN()
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-insn-defs.c.inc594 encode_dfj_insn(LoongArchInsn opc, TCGReg d, TCGReg fj)
597 tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
598 return encode_dj_slots(opc, d, fj & 0x1f);
774 encode_fdfj_insn(LoongArchInsn opc, TCGReg fd, TCGReg fj)
777 tcg_debug_assert(fj >= 0x20 && fj <= 0x3f);
778 return encode_dj_slots(opc, fd & 0x1f, fj & 0x1f);
1763 /* Emits the `fmov.d fd, fj` instruction. */
1765 tcg_out_opc_fmov_d(TCGContext *s, TCGReg fd, TCGReg fj)
1767 tcg_out32(s, encode_fdfj_insn(OPC_FMOV_D, fd, fj));
1777 /* Emits the `movfr2gr.d d, fj` instruction. */
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