Searched refs:fdk_s (Results 1 – 2 of 2) sorted by relevance
70 u8 fdk_s; /* PLL mode control: integer or fraction */ member
74 pll->fdk_s = 0x1; /* fraction */ in dphy_calc_pll_param()92 reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7); in dphy_set_pll_reg()