Searched refs:fclks (Results 1 – 7 of 7) sorted by relevance
1449 struct dm_pp_clock_levels_with_voltage *fclks) in dcn_bw_update_from_pplib_fclks() argument1453 ASSERT(fclks->num_levels); in dcn_bw_update_from_pplib_fclks()1456 vmid0p72_idx = fclks->num_levels > 2 ? fclks->num_levels - 3 : 0; in dcn_bw_update_from_pplib_fclks()1457 vnom0p8_idx = fclks->num_levels > 1 ? fclks->num_levels - 2 : 0; in dcn_bw_update_from_pplib_fclks()1458 vmax0p9_idx = fclks->num_levels > 0 ? fclks->num_levels - 1 : 0; in dcn_bw_update_from_pplib_fclks()1461 32 * (fclks->data[vmin0p65_idx].clocks_in_khz / 1000.0) / 1000.0; in dcn_bw_update_from_pplib_fclks()1464 (fclks->data[vmid0p72_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()1468 (fclks->data[vnom0p8_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()1472 (fclks->data[vmax0p9_idx].clocks_in_khz / 1000.0) in dcn_bw_update_from_pplib_fclks()
170 const struct mtk_fixed_clk *fclks; member
312 return priv->tree->fclks[clk->id].rate; in mtk_topckgen_get_rate()
548 .fclks = top_fixed_clks,
730 .fclks = top_fixed_clks,
1315 struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; in dcn10_resource_construct() local1504 ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); in dcn10_resource_construct()1509 res = verify_clock_values(&fclks); in dcn10_resource_construct()1512 dcn_bw_update_from_pplib_fclks(dc, &fclks); in dcn10_resource_construct()
639 struct dm_pp_clock_levels_with_voltage *fclks);