1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 4 * Terry Lv <r65388@freescale.com> 5 */ 6 7 #include <common.h> 8 #include <ahci.h> 9 #include <dm.h> 10 #include <dwc_ahsata.h> 11 #include <fis.h> 12 #include <libata.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <sata.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <linux/bitops.h> 20 #include <linux/ctype.h> 21 #include <linux/errno.h> 22 #include "dwc_ahsata_priv.h" 23 24 struct sata_port_regs { 25 u32 clb; 26 u32 clbu; 27 u32 fb; 28 u32 fbu; 29 u32 is; 30 u32 ie; 31 u32 cmd; 32 u32 res1[1]; 33 u32 tfd; 34 u32 sig; 35 u32 ssts; 36 u32 sctl; 37 u32 serr; 38 u32 sact; 39 u32 ci; 40 u32 sntf; 41 u32 res2[1]; 42 u32 dmacr; 43 u32 res3[1]; 44 u32 phycr; 45 u32 physr; 46 }; 47 48 struct sata_host_regs { 49 u32 cap; 50 u32 ghc; 51 u32 is; 52 u32 pi; 53 u32 vs; 54 u32 ccc_ctl; 55 u32 ccc_ports; 56 u32 res1[2]; 57 u32 cap2; 58 u32 res2[30]; 59 u32 bistafr; 60 u32 bistcr; 61 u32 bistfctr; 62 u32 bistsr; 63 u32 bistdecr; 64 u32 res3[2]; 65 u32 oobr; 66 u32 res4[8]; 67 u32 timer1ms; 68 u32 res5[1]; 69 u32 gparam1r; 70 u32 gparam2r; 71 u32 pparamr; 72 u32 testr; 73 u32 versionr; 74 u32 idr; 75 }; 76 77 #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024) 78 #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG) 79 80 #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0) 81 ahci_port_base(void __iomem * base,u32 port)82 static inline void __iomem *ahci_port_base(void __iomem *base, u32 port) 83 { 84 return base + 0x100 + (port * 0x80); 85 } 86 waiting_for_cmd_completed(u8 * offset,int timeout_msec,u32 sign)87 static int waiting_for_cmd_completed(u8 *offset, 88 int timeout_msec, 89 u32 sign) 90 { 91 int i; 92 u32 status; 93 94 for (i = 0; 95 ((status = readl(offset)) & sign) && i < timeout_msec; 96 ++i) 97 mdelay(1); 98 99 return (i < timeout_msec) ? 0 : -1; 100 } 101 ahci_setup_oobr(struct ahci_uc_priv * uc_priv,int clk)102 static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) 103 { 104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 105 106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); 107 writel(0x02060b14, &host_mmio->oobr); 108 109 return 0; 110 } 111 ahci_host_init(struct ahci_uc_priv * uc_priv)112 static int ahci_host_init(struct ahci_uc_priv *uc_priv) 113 { 114 u32 tmp, cap_save, num_ports; 115 int i, j, timeout = 1000; 116 struct sata_port_regs *port_mmio = NULL; 117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 118 int clk = mxc_get_clock(MXC_SATA_CLK); 119 120 cap_save = readl(&host_mmio->cap); 121 cap_save |= SATA_HOST_CAP_SSS; 122 123 /* global controller reset */ 124 tmp = readl(&host_mmio->ghc); 125 if ((tmp & SATA_HOST_GHC_HR) == 0) 126 writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc); 127 128 while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout) 129 ; 130 131 if (timeout <= 0) { 132 debug("controller reset failed (0x%x)\n", tmp); 133 return -1; 134 } 135 136 /* Set timer 1ms */ 137 writel(clk / 1000, &host_mmio->timer1ms); 138 139 ahci_setup_oobr(uc_priv, 0); 140 141 writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc); 142 writel(cap_save, &host_mmio->cap); 143 num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1; 144 writel_with_flush((1 << num_ports) - 1, &host_mmio->pi); 145 146 /* 147 * Determine which Ports are implemented by the DWC_ahsata, 148 * by reading the PI register. This bit map value aids the 149 * software to determine how many Ports are available and 150 * which Port registers need to be initialized. 151 */ 152 uc_priv->cap = readl(&host_mmio->cap); 153 uc_priv->port_map = readl(&host_mmio->pi); 154 155 /* Determine how many command slots the HBA supports */ 156 uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1; 157 158 debug("cap 0x%x port_map 0x%x n_ports %d\n", 159 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); 160 161 for (i = 0; i < uc_priv->n_ports; i++) { 162 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); 163 port_mmio = uc_priv->port[i].port_mmio; 164 165 /* Ensure that the DWC_ahsata is in idle state */ 166 tmp = readl(&port_mmio->cmd); 167 168 /* 169 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR 170 * are all cleared, the Port is in an idle state. 171 */ 172 if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR | 173 SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) { 174 175 /* 176 * System software places a Port into the idle state by 177 * clearing P#CMD.ST and waiting for P#CMD.CR to return 178 * 0 when read. 179 */ 180 tmp &= ~SATA_PORT_CMD_ST; 181 writel_with_flush(tmp, &port_mmio->cmd); 182 183 /* 184 * spec says 500 msecs for each bit, so 185 * this is slightly incorrect. 186 */ 187 mdelay(500); 188 189 timeout = 1000; 190 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) 191 && --timeout) 192 ; 193 194 if (timeout <= 0) { 195 debug("port reset failed (0x%x)\n", tmp); 196 return -1; 197 } 198 } 199 200 /* Spin-up device */ 201 tmp = readl(&port_mmio->cmd); 202 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); 203 204 /* Wait for spin-up to finish */ 205 timeout = 1000; 206 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) 207 && --timeout) 208 ; 209 if (timeout <= 0) { 210 debug("Spin-Up can't finish!\n"); 211 return -1; 212 } 213 214 for (j = 0; j < 100; ++j) { 215 mdelay(10); 216 tmp = readl(&port_mmio->ssts); 217 if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) || 218 ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1)) 219 break; 220 } 221 222 /* Wait for COMINIT bit 26 (DIAG_X) in SERR */ 223 timeout = 1000; 224 while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X) 225 && --timeout) 226 ; 227 if (timeout <= 0) { 228 debug("Can't find DIAG_X set!\n"); 229 return -1; 230 } 231 232 /* 233 * For each implemented Port, clear the P#SERR 234 * register, by writing ones to each implemented\ 235 * bit location. 236 */ 237 tmp = readl(&port_mmio->serr); 238 debug("P#SERR 0x%x\n", 239 tmp); 240 writel(tmp, &port_mmio->serr); 241 242 /* Ack any pending irq events for this port */ 243 tmp = readl(&host_mmio->is); 244 debug("IS 0x%x\n", tmp); 245 if (tmp) 246 writel(tmp, &host_mmio->is); 247 248 writel(1 << i, &host_mmio->is); 249 250 /* set irq mask (enables interrupts) */ 251 writel(DEF_PORT_IRQ, &port_mmio->ie); 252 253 /* register linkup ports */ 254 tmp = readl(&port_mmio->ssts); 255 debug("Port %d status: 0x%x\n", i, tmp); 256 if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03) 257 uc_priv->link_port_map |= (0x01 << i); 258 } 259 260 tmp = readl(&host_mmio->ghc); 261 debug("GHC 0x%x\n", tmp); 262 writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc); 263 tmp = readl(&host_mmio->ghc); 264 debug("GHC 0x%x\n", tmp); 265 266 return 0; 267 } 268 ahci_print_info(struct ahci_uc_priv * uc_priv)269 static void ahci_print_info(struct ahci_uc_priv *uc_priv) 270 { 271 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 272 u32 vers, cap, impl, speed; 273 const char *speed_s; 274 const char *scc_s; 275 276 vers = readl(&host_mmio->vs); 277 cap = uc_priv->cap; 278 impl = uc_priv->port_map; 279 280 speed = (cap & SATA_HOST_CAP_ISS_MASK) 281 >> SATA_HOST_CAP_ISS_OFFSET; 282 if (speed == 1) 283 speed_s = "1.5"; 284 else if (speed == 2) 285 speed_s = "3"; 286 else 287 speed_s = "?"; 288 289 scc_s = "SATA"; 290 291 printf("AHCI %02x%02x.%02x%02x " 292 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 293 (vers >> 24) & 0xff, 294 (vers >> 16) & 0xff, 295 (vers >> 8) & 0xff, 296 vers & 0xff, 297 ((cap >> 8) & 0x1f) + 1, 298 (cap & 0x1f) + 1, 299 speed_s, 300 impl, 301 scc_s); 302 303 printf("flags: " 304 "%s%s%s%s%s%s" 305 "%s%s%s%s%s%s%s\n", 306 cap & (1 << 31) ? "64bit " : "", 307 cap & (1 << 30) ? "ncq " : "", 308 cap & (1 << 28) ? "ilck " : "", 309 cap & (1 << 27) ? "stag " : "", 310 cap & (1 << 26) ? "pm " : "", 311 cap & (1 << 25) ? "led " : "", 312 cap & (1 << 24) ? "clo " : "", 313 cap & (1 << 19) ? "nz " : "", 314 cap & (1 << 18) ? "only " : "", 315 cap & (1 << 17) ? "pmp " : "", 316 cap & (1 << 15) ? "pio " : "", 317 cap & (1 << 14) ? "slum " : "", 318 cap & (1 << 13) ? "part " : ""); 319 } 320 ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)321 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, 322 unsigned char *buf, int buf_len) 323 { 324 struct ahci_ioports *pp = &uc_priv->port[port]; 325 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 326 u32 sg_count, max_bytes; 327 int i; 328 329 max_bytes = MAX_DATA_BYTES_PER_SG; 330 sg_count = ((buf_len - 1) / max_bytes) + 1; 331 if (sg_count > AHCI_MAX_SG) { 332 printf("Error:Too much sg!\n"); 333 return -1; 334 } 335 336 for (i = 0; i < sg_count; i++) { 337 ahci_sg->addr = 338 cpu_to_le32((u32)buf + i * max_bytes); 339 ahci_sg->addr_hi = 0; 340 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 341 (buf_len < max_bytes 342 ? (buf_len - 1) 343 : (max_bytes - 1))); 344 ahci_sg++; 345 buf_len -= max_bytes; 346 } 347 348 return sg_count; 349 } 350 ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 cmd_slot,u32 opts)351 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) 352 { 353 struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + 354 AHCI_CMD_SLOT_SZ * cmd_slot); 355 356 memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); 357 cmd_hdr->opts = cpu_to_le32(opts); 358 cmd_hdr->status = 0; 359 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); 360 #ifdef CONFIG_PHYS_64BIT 361 pp->cmd_slot->tbl_addr_hi = 362 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); 363 #endif 364 } 365 366 #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0) 367 ahci_exec_ata_cmd(struct ahci_uc_priv * uc_priv,u8 port,struct sata_fis_h2d * cfis,u8 * buf,u32 buf_len,s32 is_write)368 static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, 369 struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len, 370 s32 is_write) 371 { 372 struct ahci_ioports *pp = &uc_priv->port[port]; 373 struct sata_port_regs *port_mmio = pp->port_mmio; 374 u32 opts; 375 int sg_count = 0, cmd_slot = 0; 376 377 cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci)); 378 if (32 == cmd_slot) { 379 printf("Can't find empty command slot!\n"); 380 return 0; 381 } 382 383 /* Check xfer length */ 384 if (buf_len > MAX_BYTES_PER_TRANS) { 385 printf("Max transfer length is %dB\n\r", 386 MAX_BYTES_PER_TRANS); 387 return 0; 388 } 389 390 memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d)); 391 if (buf && buf_len) 392 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len); 393 opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16); 394 if (is_write) { 395 opts |= 0x40; 396 flush_cache((ulong)buf, buf_len); 397 } 398 ahci_fill_cmd_slot(pp, cmd_slot, opts); 399 400 flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); 401 writel_with_flush(1 << cmd_slot, &port_mmio->ci); 402 403 if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, 404 0x1 << cmd_slot)) { 405 printf("timeout exit!\n"); 406 return -1; 407 } 408 invalidate_dcache_range((int)(pp->cmd_slot), 409 (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); 410 debug("ahci_exec_ata_cmd: %d byte transferred.\n", 411 pp->cmd_slot->status); 412 if (!is_write) 413 invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len); 414 415 return buf_len; 416 } 417 ahci_set_feature(struct ahci_uc_priv * uc_priv,u8 port)418 static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port) 419 { 420 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 421 struct sata_fis_h2d *cfis = &h2d; 422 423 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 424 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 425 cfis->pm_port_c = 1 << 7; 426 cfis->command = ATA_CMD_SET_FEATURES; 427 cfis->features = SETFEATURES_XFER; 428 cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e; 429 430 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD); 431 } 432 ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)433 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) 434 { 435 struct ahci_ioports *pp = &uc_priv->port[port]; 436 struct sata_port_regs *port_mmio = pp->port_mmio; 437 u32 port_status; 438 u32 mem; 439 int timeout = 10000000; 440 441 debug("Enter start port: %d\n", port); 442 port_status = readl(&port_mmio->ssts); 443 debug("Port %d status: %x\n", port, port_status); 444 if ((port_status & 0xf) != 0x03) { 445 printf("No Link on this port!\n"); 446 return -1; 447 } 448 449 mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); 450 if (!mem) { 451 free(pp); 452 printf("No mem for table!\n"); 453 return -ENOMEM; 454 } 455 456 mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ 457 memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); 458 459 /* 460 * First item in chunk of DMA memory: 32-slot command table, 461 * 32 bytes each in size 462 */ 463 pp->cmd_slot = (struct ahci_cmd_hdr *)mem; 464 debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); 465 mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); 466 467 /* 468 * Second item: Received-FIS area, 256-Byte aligned 469 */ 470 pp->rx_fis = mem; 471 mem += AHCI_RX_FIS_SZ; 472 473 /* 474 * Third item: data area for storing a single command 475 * and its scatter-gather table 476 */ 477 pp->cmd_tbl = mem; 478 debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); 479 480 mem += AHCI_CMD_TBL_HDR; 481 482 writel_with_flush(0x00004444, &port_mmio->dmacr); 483 pp->cmd_tbl_sg = (struct ahci_sg *)mem; 484 writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); 485 writel_with_flush(pp->rx_fis, &port_mmio->fb); 486 487 /* Enable FRE */ 488 writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), 489 &port_mmio->cmd); 490 491 /* Wait device ready */ 492 while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR | 493 SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY)) 494 && --timeout) 495 ; 496 if (timeout <= 0) { 497 debug("Device not ready for BSY, DRQ and" 498 "ERR in TFD!\n"); 499 return -1; 500 } 501 502 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 503 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 504 PORT_CMD_START, &port_mmio->cmd); 505 506 debug("Exit start port %d\n", port); 507 508 return 0; 509 } 510 dwc_ahsata_print_info(struct blk_desc * pdev)511 static void dwc_ahsata_print_info(struct blk_desc *pdev) 512 { 513 printf("SATA Device Info:\n\r"); 514 #ifdef CONFIG_SYS_64BIT_LBA 515 printf("S/N: %s\n\rProduct model number: %s\n\r" 516 "Firmware version: %s\n\rCapacity: %lld sectors\n\r", 517 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 518 #else 519 printf("S/N: %s\n\rProduct model number: %s\n\r" 520 "Firmware version: %s\n\rCapacity: %ld sectors\n\r", 521 pdev->product, pdev->vendor, pdev->revision, pdev->lba); 522 #endif 523 } 524 dwc_ahsata_identify(struct ahci_uc_priv * uc_priv,u16 * id)525 static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id) 526 { 527 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 528 struct sata_fis_h2d *cfis = &h2d; 529 u8 port = uc_priv->hard_port_no; 530 531 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 532 533 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 534 cfis->pm_port_c = 0x80; /* is command */ 535 cfis->command = ATA_CMD_ID_ATA; 536 537 ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2, 538 READ_CMD); 539 ata_swap_buf_le16(id, ATA_ID_WORDS); 540 } 541 dwc_ahsata_xfer_mode(struct ahci_uc_priv * uc_priv,u16 * id)542 static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id) 543 { 544 uc_priv->pio_mask = id[ATA_ID_PIO_MODES]; 545 uc_priv->udma_mask = id[ATA_ID_UDMA_MODES]; 546 debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask); 547 } 548 dwc_ahsata_rw_cmd(struct ahci_uc_priv * uc_priv,u32 start,u32 blkcnt,u8 * buffer,int is_write)549 static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start, 550 u32 blkcnt, u8 *buffer, int is_write) 551 { 552 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 553 struct sata_fis_h2d *cfis = &h2d; 554 u8 port = uc_priv->hard_port_no; 555 u32 block; 556 557 block = start; 558 559 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 560 561 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 562 cfis->pm_port_c = 0x80; /* is command */ 563 cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ; 564 cfis->device = ATA_LBA; 565 566 cfis->device |= (block >> 24) & 0xf; 567 cfis->lba_high = (block >> 16) & 0xff; 568 cfis->lba_mid = (block >> 8) & 0xff; 569 cfis->lba_low = block & 0xff; 570 cfis->sector_count = (u8)(blkcnt & 0xff); 571 572 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 573 ATA_SECT_SIZE * blkcnt, is_write) > 0) 574 return blkcnt; 575 else 576 return 0; 577 } 578 dwc_ahsata_flush_cache(struct ahci_uc_priv * uc_priv)579 static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv) 580 { 581 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 582 struct sata_fis_h2d *cfis = &h2d; 583 u8 port = uc_priv->hard_port_no; 584 585 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 586 587 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 588 cfis->pm_port_c = 0x80; /* is command */ 589 cfis->command = ATA_CMD_FLUSH; 590 591 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 592 } 593 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv * uc_priv,u32 start,lbaint_t blkcnt,u8 * buffer,int is_write)594 static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start, 595 lbaint_t blkcnt, u8 *buffer, int is_write) 596 { 597 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 598 struct sata_fis_h2d *cfis = &h2d; 599 u8 port = uc_priv->hard_port_no; 600 u64 block; 601 602 block = (u64)start; 603 604 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 605 606 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 607 cfis->pm_port_c = 0x80; /* is command */ 608 609 cfis->command = (is_write) ? ATA_CMD_WRITE_EXT 610 : ATA_CMD_READ_EXT; 611 612 cfis->lba_high_exp = (block >> 40) & 0xff; 613 cfis->lba_mid_exp = (block >> 32) & 0xff; 614 cfis->lba_low_exp = (block >> 24) & 0xff; 615 cfis->lba_high = (block >> 16) & 0xff; 616 cfis->lba_mid = (block >> 8) & 0xff; 617 cfis->lba_low = block & 0xff; 618 cfis->device = ATA_LBA; 619 cfis->sector_count_exp = (blkcnt >> 8) & 0xff; 620 cfis->sector_count = blkcnt & 0xff; 621 622 if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer, 623 ATA_SECT_SIZE * blkcnt, is_write) > 0) 624 return blkcnt; 625 else 626 return 0; 627 } 628 dwc_ahsata_flush_cache_ext(struct ahci_uc_priv * uc_priv)629 static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv) 630 { 631 struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN); 632 struct sata_fis_h2d *cfis = &h2d; 633 u8 port = uc_priv->hard_port_no; 634 635 memset(cfis, 0, sizeof(struct sata_fis_h2d)); 636 637 cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D; 638 cfis->pm_port_c = 0x80; /* is command */ 639 cfis->command = ATA_CMD_FLUSH_EXT; 640 641 ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0); 642 } 643 dwc_ahsata_init_wcache(struct ahci_uc_priv * uc_priv,u16 * id)644 static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id) 645 { 646 if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id)) 647 uc_priv->flags |= SATA_FLAG_WCACHE; 648 if (ata_id_has_flush(id)) 649 uc_priv->flags |= SATA_FLAG_FLUSH; 650 if (ata_id_has_flush_ext(id)) 651 uc_priv->flags |= SATA_FLAG_FLUSH_EXT; 652 } 653 ata_low_level_rw_lba48(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)654 static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr, 655 lbaint_t blkcnt, const void *buffer, 656 int is_write) 657 { 658 u32 start, blks; 659 u8 *addr; 660 int max_blks; 661 662 start = blknr; 663 blks = blkcnt; 664 addr = (u8 *)buffer; 665 666 max_blks = ATA_MAX_SECTORS_LBA48; 667 668 do { 669 if (blks > max_blks) { 670 if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, 671 max_blks, addr, 672 is_write)) 673 return 0; 674 start += max_blks; 675 blks -= max_blks; 676 addr += ATA_SECT_SIZE * max_blks; 677 } else { 678 if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks, 679 addr, is_write)) 680 return 0; 681 start += blks; 682 blks = 0; 683 addr += ATA_SECT_SIZE * blks; 684 } 685 } while (blks != 0); 686 687 return blkcnt; 688 } 689 ata_low_level_rw_lba28(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)690 static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr, 691 lbaint_t blkcnt, const void *buffer, 692 int is_write) 693 { 694 u32 start, blks; 695 u8 *addr; 696 int max_blks; 697 698 start = blknr; 699 blks = blkcnt; 700 addr = (u8 *)buffer; 701 702 max_blks = ATA_MAX_SECTORS; 703 do { 704 if (blks > max_blks) { 705 if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start, 706 max_blks, addr, 707 is_write)) 708 return 0; 709 start += max_blks; 710 blks -= max_blks; 711 addr += ATA_SECT_SIZE * max_blks; 712 } else { 713 if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks, 714 addr, is_write)) 715 return 0; 716 start += blks; 717 blks = 0; 718 addr += ATA_SECT_SIZE * blks; 719 } 720 } while (blks != 0); 721 722 return blkcnt; 723 } 724 dwc_ahci_start_ports(struct ahci_uc_priv * uc_priv)725 static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv) 726 { 727 u32 linkmap; 728 int i; 729 730 linkmap = uc_priv->link_port_map; 731 732 if (0 == linkmap) { 733 printf("No port device detected!\n"); 734 return -ENXIO; 735 } 736 737 for (i = 0; i < uc_priv->n_ports; i++) { 738 if ((linkmap >> i) && ((linkmap >> i) & 0x01)) { 739 if (ahci_port_start(uc_priv, (u8)i)) { 740 printf("Can not start port %d\n", i); 741 return 1; 742 } 743 uc_priv->hard_port_no = i; 744 break; 745 } 746 } 747 748 return 0; 749 } 750 dwc_ahsata_scan_common(struct ahci_uc_priv * uc_priv,struct blk_desc * pdev)751 static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv, 752 struct blk_desc *pdev) 753 { 754 u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 }; 755 u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 }; 756 u8 product[ATA_ID_PROD_LEN + 1] = { 0 }; 757 u64 n_sectors; 758 u8 port = uc_priv->hard_port_no; 759 ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS); 760 761 /* Identify device to get information */ 762 dwc_ahsata_identify(uc_priv, id); 763 764 /* Serial number */ 765 ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial)); 766 memcpy(pdev->product, serial, sizeof(serial)); 767 768 /* Firmware version */ 769 ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware)); 770 memcpy(pdev->revision, firmware, sizeof(firmware)); 771 772 /* Product model */ 773 ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product)); 774 memcpy(pdev->vendor, product, sizeof(product)); 775 776 /* Totoal sectors */ 777 n_sectors = ata_id_n_sectors(id); 778 pdev->lba = (u32)n_sectors; 779 780 pdev->type = DEV_TYPE_HARDDISK; 781 pdev->blksz = ATA_SECT_SIZE; 782 pdev->lun = 0; 783 784 /* Check if support LBA48 */ 785 if (ata_id_has_lba48(id)) { 786 pdev->lba48 = 1; 787 debug("Device support LBA48\n\r"); 788 } 789 790 /* Get the NCQ queue depth from device */ 791 uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK); 792 uc_priv->flags |= ata_id_queue_depth(id); 793 794 /* Get the xfer mode from device */ 795 dwc_ahsata_xfer_mode(uc_priv, id); 796 797 /* Get the write cache status from device */ 798 dwc_ahsata_init_wcache(uc_priv, id); 799 800 /* Set the xfer mode to highest speed */ 801 ahci_set_feature(uc_priv, port); 802 803 dwc_ahsata_print_info(pdev); 804 805 return 0; 806 } 807 808 /* 809 * SATA interface between low level driver and command layer 810 */ sata_read_common(struct ahci_uc_priv * uc_priv,struct blk_desc * desc,ulong blknr,lbaint_t blkcnt,void * buffer)811 static ulong sata_read_common(struct ahci_uc_priv *uc_priv, 812 struct blk_desc *desc, ulong blknr, 813 lbaint_t blkcnt, void *buffer) 814 { 815 u32 rc; 816 817 if (desc->lba48) 818 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 819 READ_CMD); 820 else 821 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 822 READ_CMD); 823 824 return rc; 825 } 826 sata_write_common(struct ahci_uc_priv * uc_priv,struct blk_desc * desc,ulong blknr,lbaint_t blkcnt,const void * buffer)827 static ulong sata_write_common(struct ahci_uc_priv *uc_priv, 828 struct blk_desc *desc, ulong blknr, 829 lbaint_t blkcnt, const void *buffer) 830 { 831 u32 rc; 832 u32 flags = uc_priv->flags; 833 834 if (desc->lba48) { 835 rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer, 836 WRITE_CMD); 837 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT)) 838 dwc_ahsata_flush_cache_ext(uc_priv); 839 } else { 840 rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer, 841 WRITE_CMD); 842 if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH)) 843 dwc_ahsata_flush_cache(uc_priv); 844 } 845 846 return rc; 847 } 848 849 #if !CONFIG_IS_ENABLED(AHCI) ahci_init_one(int pdev)850 static int ahci_init_one(int pdev) 851 { 852 int rc; 853 struct ahci_uc_priv *uc_priv = NULL; 854 855 uc_priv = malloc(sizeof(struct ahci_uc_priv)); 856 memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); 857 uc_priv->dev = pdev; 858 859 uc_priv->host_flags = ATA_FLAG_SATA 860 | ATA_FLAG_NO_LEGACY 861 | ATA_FLAG_MMIO 862 | ATA_FLAG_PIO_DMA 863 | ATA_FLAG_NO_ATAPI; 864 865 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; 866 867 /* initialize adapter */ 868 rc = ahci_host_init(uc_priv); 869 if (rc) 870 goto err_out; 871 872 ahci_print_info(uc_priv); 873 874 /* Save the uc_private struct to block device struct */ 875 sata_dev_desc[pdev].priv = uc_priv; 876 877 return 0; 878 879 err_out: 880 return rc; 881 } 882 init_sata(int dev)883 int init_sata(int dev) 884 { 885 struct ahci_uc_priv *uc_priv = NULL; 886 887 #if defined(CONFIG_MX6) 888 if (!is_mx6dq() && !is_mx6dqp()) 889 return 1; 890 #endif 891 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 892 printf("The sata index %d is out of ranges\n\r", dev); 893 return -1; 894 } 895 896 ahci_init_one(dev); 897 898 uc_priv = sata_dev_desc[dev].priv; 899 900 return dwc_ahci_start_ports(uc_priv) ? 1 : 0; 901 } 902 reset_sata(int dev)903 int reset_sata(int dev) 904 { 905 struct ahci_uc_priv *uc_priv; 906 struct sata_host_regs *host_mmio; 907 908 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { 909 printf("The sata index %d is out of ranges\n\r", dev); 910 return -1; 911 } 912 913 uc_priv = sata_dev_desc[dev].priv; 914 if (NULL == uc_priv) 915 /* not initialized, so nothing to reset */ 916 return 0; 917 918 host_mmio = uc_priv->mmio_base; 919 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 920 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 921 udelay(100); 922 923 return 0; 924 } 925 sata_port_status(int dev,int port)926 int sata_port_status(int dev, int port) 927 { 928 struct sata_port_regs *port_mmio; 929 struct ahci_uc_priv *uc_priv = NULL; 930 931 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) 932 return -EINVAL; 933 934 if (sata_dev_desc[dev].priv == NULL) 935 return -ENODEV; 936 937 uc_priv = sata_dev_desc[dev].priv; 938 port_mmio = uc_priv->port[port].port_mmio; 939 940 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK; 941 } 942 943 /* 944 * SATA interface between low level driver and command layer 945 */ sata_read(int dev,ulong blknr,lbaint_t blkcnt,void * buffer)946 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) 947 { 948 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 949 950 return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, 951 buffer); 952 } 953 sata_write(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer)954 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) 955 { 956 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 957 958 return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt, 959 buffer); 960 } 961 scan_sata(int dev)962 int scan_sata(int dev) 963 { 964 struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv; 965 struct blk_desc *pdev = &sata_dev_desc[dev]; 966 967 return dwc_ahsata_scan_common(uc_priv, pdev); 968 } 969 #endif /* CONFIG_IS_ENABLED(AHCI) */ 970 971 #if CONFIG_IS_ENABLED(AHCI) 972 dwc_ahsata_port_status(struct udevice * dev,int port)973 int dwc_ahsata_port_status(struct udevice *dev, int port) 974 { 975 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 976 struct sata_port_regs *port_mmio; 977 978 port_mmio = uc_priv->port[port].port_mmio; 979 return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO; 980 } 981 dwc_ahsata_bus_reset(struct udevice * dev)982 int dwc_ahsata_bus_reset(struct udevice *dev) 983 { 984 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 985 struct sata_host_regs *host_mmio = uc_priv->mmio_base; 986 987 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR); 988 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) 989 udelay(100); 990 991 return 0; 992 } 993 dwc_ahsata_scan(struct udevice * dev)994 int dwc_ahsata_scan(struct udevice *dev) 995 { 996 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 997 struct blk_desc *desc; 998 struct udevice *blk; 999 int ret; 1000 1001 /* 1002 * Create only one block device and do detection 1003 * to make sure that there won't be a lot of 1004 * block devices created 1005 */ 1006 device_find_first_child(dev, &blk); 1007 if (!blk) { 1008 ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk", 1009 IF_TYPE_SATA, -1, 512, 0, &blk); 1010 if (ret) { 1011 debug("Can't create device\n"); 1012 return ret; 1013 } 1014 } 1015 1016 desc = dev_get_uclass_platdata(blk); 1017 ret = dwc_ahsata_scan_common(uc_priv, desc); 1018 if (ret) { 1019 debug("%s: Failed to scan bus\n", __func__); 1020 return ret; 1021 } 1022 1023 return 0; 1024 } 1025 dwc_ahsata_probe(struct udevice * dev)1026 int dwc_ahsata_probe(struct udevice *dev) 1027 { 1028 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); 1029 int ret; 1030 1031 uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 1032 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; 1033 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); 1034 1035 /* initialize adapter */ 1036 ret = ahci_host_init(uc_priv); 1037 if (ret) 1038 return ret; 1039 1040 ahci_print_info(uc_priv); 1041 1042 return dwc_ahci_start_ports(uc_priv); 1043 } 1044 dwc_ahsata_read(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,void * buffer)1045 static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr, 1046 lbaint_t blkcnt, void *buffer) 1047 { 1048 struct blk_desc *desc = dev_get_uclass_platdata(blk); 1049 struct udevice *dev = dev_get_parent(blk); 1050 struct ahci_uc_priv *uc_priv; 1051 1052 uc_priv = dev_get_uclass_priv(dev); 1053 return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer); 1054 } 1055 dwc_ahsata_write(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,const void * buffer)1056 static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr, 1057 lbaint_t blkcnt, const void *buffer) 1058 { 1059 struct blk_desc *desc = dev_get_uclass_platdata(blk); 1060 struct udevice *dev = dev_get_parent(blk); 1061 struct ahci_uc_priv *uc_priv; 1062 1063 uc_priv = dev_get_uclass_priv(dev); 1064 return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer); 1065 } 1066 1067 static const struct blk_ops dwc_ahsata_blk_ops = { 1068 .read = dwc_ahsata_read, 1069 .write = dwc_ahsata_write, 1070 }; 1071 1072 U_BOOT_DRIVER(dwc_ahsata_blk) = { 1073 .name = "dwc_ahsata_blk", 1074 .id = UCLASS_BLK, 1075 .ops = &dwc_ahsata_blk_ops, 1076 }; 1077 1078 #endif 1079