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Searched refs:exynos5_epll_div (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c102 static struct set_epll_con_val exynos5_epll_div[] = { variable
1282 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { in exynos5_set_epll_clk()
1283 if (exynos5_epll_div[i].freq_out == rate) in exynos5_set_epll_clk()
1287 if (i == ARRAY_SIZE(exynos5_epll_div)) in exynos5_set_epll_clk()
1290 epll_con_k = exynos5_epll_div[i].k_dsm << 0; in exynos5_set_epll_clk()
1291 epll_con |= exynos5_epll_div[i].en_lock_det << in exynos5_set_epll_clk()
1293 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; in exynos5_set_epll_clk()
1294 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; in exynos5_set_epll_clk()
1295 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; in exynos5_set_epll_clk()
1302 lockcnt = 3000 * exynos5_epll_div[i].p_div; in exynos5_set_epll_clk()