1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell Octeon EP (EndPoint) Ethernet Driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef _OCTEP_TX_H_ 9 #define _OCTEP_TX_H_ 10 11 #define IQ_SEND_OK 0 12 #define IQ_SEND_STOP 1 13 #define IQ_SEND_FAILED -1 14 15 #define TX_BUFTYPE_NONE 0 16 #define TX_BUFTYPE_NET 1 17 #define TX_BUFTYPE_NET_SG 2 18 #define NUM_TX_BUFTYPES 3 19 20 /* Hardware format for Scatter/Gather list 21 * 22 * 63 48|47 32|31 16|15 0 23 * ----------------------------------------- 24 * | Len 0 | Len 1 | Len 2 | Len 3 | 25 * ----------------------------------------- 26 * | Ptr 0 | 27 * ----------------------------------------- 28 * | Ptr 1 | 29 * ----------------------------------------- 30 * | Ptr 2 | 31 * ----------------------------------------- 32 * | Ptr 3 | 33 * ----------------------------------------- 34 */ 35 struct octep_tx_sglist_desc { 36 u16 len[4]; 37 dma_addr_t dma_ptr[4]; 38 }; 39 40 /* Each Scatter/Gather entry sent to hardwar hold four pointers. 41 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1' 42 * is for main skb which also goes as a gather buffer to Octeon hardware. 43 * To allocate sufficient SGLIST entries for a packet with max fragments, 44 * align by adding 3 before calcuating max SGLIST entries per packet. 45 */ 46 #define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4) 47 #define OCTEP_SGLIST_SIZE_PER_PKT \ 48 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc)) 49 50 struct octep_tx_buffer { 51 struct sk_buff *skb; 52 dma_addr_t dma; 53 struct octep_tx_sglist_desc *sglist; 54 dma_addr_t sglist_dma; 55 u8 gather; 56 }; 57 58 #define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer)) 59 60 /* Hardware interface Tx statistics */ 61 struct octep_iface_tx_stats { 62 /* Packets dropped due to excessive collisions */ 63 u64 xscol; 64 65 /* Packets dropped due to excessive deferral */ 66 u64 xsdef; 67 68 /* Packets sent that experienced multiple collisions before successful 69 * transmission 70 */ 71 u64 mcol; 72 73 /* Packets sent that experienced a single collision before successful 74 * transmission 75 */ 76 u64 scol; 77 78 /* Total octets sent on the interface */ 79 u64 octs; 80 81 /* Total frames sent on the interface */ 82 u64 pkts; 83 84 /* Packets sent with an octet count < 64 */ 85 u64 hist_lt64; 86 87 /* Packets sent with an octet count == 64 */ 88 u64 hist_eq64; 89 90 /* Packets sent with an octet count of 65–127 */ 91 u64 hist_65to127; 92 93 /* Packets sent with an octet count of 128–255 */ 94 u64 hist_128to255; 95 96 /* Packets sent with an octet count of 256–511 */ 97 u64 hist_256to511; 98 99 /* Packets sent with an octet count of 512–1023 */ 100 u64 hist_512to1023; 101 102 /* Packets sent with an octet count of 1024-1518 */ 103 u64 hist_1024to1518; 104 105 /* Packets sent with an octet count of > 1518 */ 106 u64 hist_gt1518; 107 108 /* Packets sent to a broadcast DMAC */ 109 u64 bcst; 110 111 /* Packets sent to the multicast DMAC */ 112 u64 mcst; 113 114 /* Packets sent that experienced a transmit underflow and were 115 * truncated 116 */ 117 u64 undflw; 118 119 /* Control/PAUSE packets sent */ 120 u64 ctl; 121 }; 122 123 /* Input Queue statistics. Each input queue has four stats fields. */ 124 struct octep_iq_stats { 125 /* Instructions posted to this queue. */ 126 u64 instr_posted; 127 128 /* Instructions copied by hardware for processing. */ 129 u64 instr_completed; 130 131 /* Instructions that could not be processed. */ 132 u64 instr_dropped; 133 134 /* Bytes sent through this queue. */ 135 u64 bytes_sent; 136 137 /* Gather entries sent through this queue. */ 138 u64 sgentry_sent; 139 140 /* Number of transmit failures due to TX_BUSY */ 141 u64 tx_busy; 142 143 /* Number of times the queue is restarted */ 144 u64 restart_cnt; 145 }; 146 147 /* The instruction (input) queue. 148 * The input queue is used to post raw (instruction) mode data or packet 149 * data to Octeon device from the host. Each input queue (up to 4) for 150 * a Octeon device has one such structure to represent it. 151 */ 152 struct octep_iq { 153 u32 q_no; 154 155 struct octep_device *octep_dev; 156 struct net_device *netdev; 157 struct device *dev; 158 struct netdev_queue *netdev_q; 159 160 /* Index in input ring where driver should write the next packet */ 161 u16 host_write_index; 162 163 /* Index in input ring where Octeon is expected to read next packet */ 164 u16 octep_read_index; 165 166 /* This index aids in finding the window in the queue where Octeon 167 * has read the commands. 168 */ 169 u16 flush_index; 170 171 /* Statistics for this input queue. */ 172 struct octep_iq_stats stats; 173 174 /* This field keeps track of the instructions pending in this queue. */ 175 atomic_t instr_pending; 176 177 /* Pointer to the Virtual Base addr of the input ring. */ 178 struct octep_tx_desc_hw *desc_ring; 179 180 /* DMA mapped base address of the input descriptor ring. */ 181 dma_addr_t desc_ring_dma; 182 183 /* Info of Tx buffers pending completion. */ 184 struct octep_tx_buffer *buff_info; 185 186 /* Base pointer to Scatter/Gather lists for all ring descriptors. */ 187 struct octep_tx_sglist_desc *sglist; 188 189 /* DMA mapped addr of Scatter Gather Lists */ 190 dma_addr_t sglist_dma; 191 192 /* Octeon doorbell register for the ring. */ 193 u8 __iomem *doorbell_reg; 194 195 /* Octeon instruction count register for this ring. */ 196 u8 __iomem *inst_cnt_reg; 197 198 /* interrupt level register for this ring */ 199 u8 __iomem *intr_lvl_reg; 200 201 /* Maximum no. of instructions in this queue. */ 202 u32 max_count; 203 u32 ring_size_mask; 204 205 u32 pkt_in_done; 206 u32 pkts_processed; 207 208 u32 status; 209 210 /* Number of instructions pending to be posted to Octeon. */ 211 u32 fill_cnt; 212 213 /* The max. number of instructions that can be held pending by the 214 * driver before ringing doorbell. 215 */ 216 u32 fill_threshold; 217 }; 218 219 /* Hardware Tx Instruction Header */ 220 struct octep_instr_hdr { 221 /* Data Len */ 222 u64 tlen:16; 223 224 /* Reserved */ 225 u64 rsvd:20; 226 227 /* PKIND for SDP */ 228 u64 pkind:6; 229 230 /* Front Data size */ 231 u64 fsz:6; 232 233 /* No. of entries in gather list */ 234 u64 gsz:14; 235 236 /* Gather indicator 1=gather*/ 237 u64 gather:1; 238 239 /* Reserved3 */ 240 u64 reserved3:1; 241 }; 242 243 /* Hardware Tx completion response header */ 244 struct octep_instr_resp_hdr { 245 /* Request ID */ 246 u64 rid:16; 247 248 /* PCIe port to use for response */ 249 u64 pcie_port:3; 250 251 /* Scatter indicator 1=scatter */ 252 u64 scatter:1; 253 254 /* Size of Expected result OR no. of entries in scatter list */ 255 u64 rlenssz:14; 256 257 /* Desired destination port for result */ 258 u64 dport:6; 259 260 /* Opcode Specific parameters */ 261 u64 param:8; 262 263 /* Opcode for the return packet */ 264 u64 opcode:16; 265 }; 266 267 /* 64-byte Tx instruction format. 268 * Format of instruction for a 64-byte mode input queue. 269 * 270 * only first 16-bytes (dptr and ih) are mandatory; rest are optional 271 * and filled by the driver based on firmware/hardware capabilities. 272 * These optional headers together called Front Data and its size is 273 * described by ih->fsz. 274 */ 275 struct octep_tx_desc_hw { 276 /* Pointer where the input data is available. */ 277 u64 dptr; 278 279 /* Instruction Header. */ 280 union { 281 struct octep_instr_hdr ih; 282 u64 ih64; 283 }; 284 285 /* Pointer where the response for a RAW mode packet will be written 286 * by Octeon. 287 */ 288 u64 rptr; 289 290 /* Input Instruction Response Header. */ 291 struct octep_instr_resp_hdr irh; 292 293 /* Additional headers available in a 64-byte instruction. */ 294 u64 exhdr[4]; 295 }; 296 297 #define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw)) 298 #endif /* _OCTEP_TX_H_ */ 299