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Searched refs:excvaddr (Results 1 – 25 of 27) sorted by relevance

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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_phys_mem.S33 rsr a3, excvaddr
51 rsr a3, excvaddr
70 rsr a3, excvaddr
89 rsr a3, excvaddr
107 rsr a3, excvaddr
126 rsr a3, excvaddr
H A Dtest_mmu.S91 rsr a2, excvaddr
105 rsr a2, excvaddr
156 rsr a2, excvaddr
204 rsr a2, excvaddr
236 rsr a2, excvaddr
277 rsr a2, excvaddr
297 rsr a2, excvaddr
319 rsr a2, excvaddr
374 wsr a2, excvaddr
435 rsr a2, excvaddr
[all …]
H A Dtest_load_store.S54 rsr a6, excvaddr
134 rsr a6, excvaddr
H A Dtest_cache.S53 rsr a2, excvaddr
H A Dtest_sr.S132 test_sr excvaddr, 1
H A Dfpu.h132 rsr a2, excvaddr
/openbmc/u-boot/arch/xtensa/cpu/
H A Dexceptions.c23 regs->exccause, regs->excvaddr, regs->pc); in unhandled_exception()
/openbmc/u-boot/arch/xtensa/include/asm/
H A Dptrace.h89 unsigned long excvaddr; /* 20 */ member
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc71 XTREG( 48,192,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc6217 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
6220 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
6223 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc217 XTREG(98, 392, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr,
H A Dxtensa-modules.c.inc11356 { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
11359 { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
11362 { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
12439 return 203; /* xsr.excvaddr */
12639 return 201; /* rsr.excvaddr */
12774 return 202; /* wsr.excvaddr */
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc107 XTREG( 83,332,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9198 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
9201 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
9204 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc124 XTREG(99, 396, 32, 4, 4, 0x02ee, 0x0007, -2, 2, 0x1000, excvaddr, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12002 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
12005 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
12008 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc121 XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc27239 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
27242 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
27245 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc116 XTREG( 92,368,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11371 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
11374 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
11377 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc153 XTREG(118,520,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc157 XTREG(118,536,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16624 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
16627 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
16630 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
/openbmc/qemu/target/xtensa/core-fsf/
H A Dxtensa-modules.c.inc8229 { "rsr.excvaddr", 130 /* xt_iclass_rsr.excvaddr */,
8232 { "wsr.excvaddr", 131 /* xt_iclass_wsr.excvaddr */,
8235 { "xsr.excvaddr", 132 /* xt_iclass_xsr.excvaddr */,
8898 return 174; /* xsr.excvaddr */
9045 return 172; /* rsr.excvaddr */
9142 return 173; /* wsr.excvaddr */
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc291 XTREG(212,1968,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)

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