/openbmc/linux/drivers/net/ethernet/huawei/hinic/ |
H A D | hinic_hw_eqs.c | 49 ((eq)->virt_addr[(idx) / (eq)->num_elem_in_pg] + \ 58 #define GET_CURR_AEQ_ELEM(eq) GET_AEQ_ELEM(eq, (eq)->cons_idx) argument 60 #define GET_CURR_CEQ_ELEM(eq) GET_CEQ_ELEM(eq, (eq)->cons_idx) argument 270 if (eq->cons_idx == eq->q_len) { in aeq_irq_handler() 272 eq->wrapped = !eq->wrapped; in aeq_irq_handler() 334 if (eq->cons_idx == eq->q_len) { in ceq_irq_handler() 336 eq->wrapped = !eq->wrapped; in ceq_irq_handler() 797 snprintf(eq->irq_name, sizeof(eq->irq_name), "hinic_aeq%d@pci:%s", eq->q_id, in init_eq() 801 snprintf(eq->irq_name, sizeof(eq->irq_name), "hinic_ceq%d@pci:%s", eq->q_id, in init_eq() 826 free_irq(eq->msix_entry.vector, eq); in remove_eq() [all …]
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/openbmc/linux/drivers/infiniband/hw/erdma/ |
H A D | erdma_eq.c | 24 u64 *eqe = get_queue_entry(eq->qbuf, eq->ci, eq->depth, EQE_SHIFT); in get_next_valid_eqe() 27 return owner ^ !!(eq->ci & eq->depth) ? eqe : NULL; in get_next_valid_eqe() 91 eq->qbuf = in erdma_aeq_init() 94 if (!eq->qbuf) in erdma_aeq_init() 102 eq->db_record = (u64 *)(eq->qbuf + buf_size); in erdma_aeq_init() 120 WARPPED_BUFSIZE(eq->depth << EQE_SHIFT), eq->qbuf, in erdma_aeq_destroy() 231 struct erdma_eq *eq = &dev->ceqs[ceqn].eq; in erdma_ceq_init_one() local 235 eq->qbuf = in erdma_ceq_init_one() 248 eq->db_record = (u64 *)(eq->qbuf + buf_size); in erdma_ceq_init_one() 249 eq->ci = 0; in erdma_ceq_init_one() [all …]
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/ |
H A D | eq.c | 617 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb); in setup_async_eq() 630 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb); in cleanup_async_eq() 755 if (!eq) in mlx5_eq_create_generic() 765 return eq; in mlx5_eq_create_generic() 978 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb); in destroy_comp_eq() 983 kfree(eq); in destroy_comp_eq() 1027 if (!eq) { in create_comp_eq() 1047 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb); in create_comp_eq() 1062 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb); in create_comp_eq() 1078 if (eq) { in mlx5_comp_eqn_get() [all …]
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/openbmc/linux/sound/pci/au88x0/ |
H A D | au88x0_eq.c | 495 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_GetLeftGain() local 506 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetLeftGain() local 520 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_GetRightGain() local 531 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetRightGain() local 547 eqlzr_t *eq = &(vortex->eq); 568 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetAllBandsFromActiveCoeffSet() local 579 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetAllBands() local 597 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetA3dBypassGain() local 613 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_ProgramA3dBypassGain() local 633 eqlzr_t *eq = &(vortex->eq); in vortex_Eqlzr_SetBypass() local [all …]
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/openbmc/linux/drivers/infiniband/hw/mthca/ |
H A D | mthca_eq.c | 184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci() 237 eqe = get_eqe(eq, eq->cons_index); in next_eqe_sw() 363 ++eq->cons_index; in mthca_eq_int() 379 set_eq_ci(dev, eq, eq->cons_index); in mthca_eq_int() 424 tavor_set_eq_ci(dev, eq, eq->cons_index); in mthca_tavor_msi_x_interrupt() 458 arbel_set_eq_ci(dev, eq, eq->cons_index); in mthca_arbel_msi_x_interrupt() 478 eq->dev = dev; in mthca_create_eq() 482 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list), in mthca_create_eq() 523 &eq->mr); in mthca_create_eq() 554 eq->eqn_mask = swab32(1 << eq->eqn); in mthca_create_eq() [all …]
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/openbmc/qemu/tests/tcg/xtensa/ |
H A D | test_rst0.S | 11 assert eq, a5, a6 13 assert eq, a2, a6 15 assert eq, a3, a6 24 assert eq, a5, a6 26 assert eq, a2, a6 28 assert eq, a3, a6 37 assert eq, a5, a6 39 assert eq, a2, a6 41 assert eq, a3, a6 50 assert eq, a5, a6 [all …]
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H A D | test_rem.S | 13 assert eq, a5, a6 15 assert eq, a2, a6 17 assert eq, a4, a6 26 assert eq, a5, a6 28 assert eq, a2, a6 30 assert eq, a4, a6 39 assert eq, a5, a6 41 assert eq, a2, a6 43 assert eq, a4, a6 52 assert eq, a5, a6 [all …]
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H A D | test_quo.S | 13 assert eq, a5, a6 15 assert eq, a2, a6 17 assert eq, a4, a6 26 assert eq, a5, a6 28 assert eq, a2, a6 30 assert eq, a4, a6 39 assert eq, a5, a6 41 assert eq, a2, a6 43 assert eq, a4, a6 52 assert eq, a5, a6 [all …]
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H A D | test_lsc.S | 22 assert eq, a2, a3 25 assert eq, a2, a3 28 assert eq, a2, a3 31 assert eq, a2, a3 56 assert eq, a2, a3 59 assert eq, a4, a3 62 assert eq, a4, a3 65 assert eq, a4, a3 87 assert eq, a2, a3 90 assert eq, a2, a3 [all …]
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H A D | test_mul16.S | 13 assert eq, a5, a6 15 assert eq, a2, a6 17 assert eq, a3, a6 26 assert eq, a5, a6 28 assert eq, a2, a6 30 assert eq, a3, a6 39 assert eq, a5, a6 41 assert eq, a2, a6 43 assert eq, a3, a6 52 assert eq, a5, a6 [all …]
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H A D | test_phys_mem.S | 34 assert eq, a2, a3 36 assert eq, a2, a3 39 assert eq, a2, a3 52 assert eq, a2, a3 55 assert eq, a2, a3 58 assert eq, a2, a3 71 assert eq, a2, a3 74 assert eq, a2, a3 77 assert eq, a2, a3 90 assert eq, a2, a3 [all …]
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H A D | test_sext.S | 11 assert eq, a3, a4 16 assert eq, a3, a4 21 assert eq, a3, a4 26 assert eq, a3, a4 31 assert eq, a3, a4 36 assert eq, a3, a4 41 assert eq, a3, a4 46 assert eq, a3, a4 51 assert eq, a3, a4 56 assert eq, a3, a4 [all …]
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H A D | test_mmu.S | 55 assert eq, a1, a3 56 assert eq, a2, a3 61 assert eq, a1, a3 62 assert eq, a2, a3 67 assert eq, a1, a3 69 assert eq, a2, a3 92 assert eq, a2, a3 95 assert eq, a2, a3 106 assert eq, a2, a3 109 assert eq, a2, a3 [all …]
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H A D | test_max.S | 12 assert eq, a5, a4 18 assert eq, a5, a4 24 assert eq, a2, a4 30 assert eq, a3, a4 36 assert eq, a2, a4 42 assert eq, a3, a4 50 assert eq, a5, a4 56 assert eq, a5, a4 62 assert eq, a2, a4 68 assert eq, a3, a4 [all …]
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H A D | test_min.S | 12 assert eq, a5, a4 18 assert eq, a5, a4 24 assert eq, a2, a4 30 assert eq, a3, a4 36 assert eq, a2, a4 42 assert eq, a3, a4 50 assert eq, a5, a4 56 assert eq, a5, a4 62 assert eq, a2, a4 68 assert eq, a3, a4 [all …]
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H A D | test_nsa.S | 11 assert eq, a3, a4 16 assert eq, a3, a4 21 assert eq, a3, a2 26 assert eq, a3, a2 31 assert eq, a3, a4 36 assert eq, a3, a4 43 assert eq, a3, a4 48 assert eq, a3, a4 53 assert eq, a3, a2 58 assert eq, a3, a2
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H A D | test_windowed.S | 38 assert eq, a2, a3 44 assert eq, a2, a3 47 assert eq, a2, a3 55 assert eq, a2, a3 58 assert eq, a2, a3 102 assert eq, a2, a3 108 assert eq, a2, a3 111 assert eq, a2, a3 118 assert eq, a2, a3 151 assert eq, a2, a3 [all …]
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H A D | test_load_store.S | 19 assert eq, a5, a6 44 assert eq, a5, a6 50 assert eq, a6, a7 53 assert eq, a6, a7 55 assert eq, a6, a3 56 assert eq, a5, a4 75 assert eq, a5, a6 97 assert eq, a5, a6 101 assert eq, a5, a6 130 assert eq, a6, a7 [all …]
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H A D | test_clamps.S | 11 assert eq, a3, a4 16 assert eq, a3, a4 21 assert eq, a3, a4 26 assert eq, a3, a2 31 assert eq, a3, a2 36 assert eq, a3, a2 41 assert eq, a3, a2
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/ |
H A D | eq.h | 51 static inline u32 eq_get_size(struct mlx5_eq *eq) in eq_get_size() argument 53 return eq->fbc.sz_m1 + 1; in eq_get_size() 58 return mlx5_frag_buf_get_wqe(&eq->fbc, entry); in get_eqe() 61 static inline struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) in next_eqe_sw() argument 63 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & eq->fbc.sz_m1); in next_eqe_sw() 65 return (eqe->owner ^ (eq->cons_index >> eq->fbc.log_sz)) & 1 ? NULL : eqe; in next_eqe_sw() 68 static inline void eq_update_ci(struct mlx5_eq *eq, int arm) in eq_update_ci() argument 70 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); in eq_update_ci() 71 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); in eq_update_ci() 83 int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq); [all …]
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx4/ |
H A D | eq.c | 241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; in mlx4_set_eq_affinity_hint() local 543 eq->eqn, eq->cons_index, ret); in mlx4_eq_int() 573 eq->eqn, eq->cons_index, ret); in mlx4_eq_int() 698 eq->eqn, eq->cons_index, ret); in mlx4_eq_int() 783 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int() 808 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int() 820 eq->cons_index, eqe->owner, eq->nent, in mlx4_eq_int() 1023 eq->doorbell = mlx4_get_eq_uar(dev, eq); in mlx4_create_eq() 1226 struct mlx4_eq *eq = &priv->eq_table.eq[i]; in mlx4_init_eq_table() local 1473 eq = &priv->eq_table.eq[requested_vector]; in mlx4_assign_eq() [all …]
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/openbmc/linux/drivers/scsi/elx/efct/ |
H A D | efct_hw_queues.c | 35 if (!eq) { in efct_hw_init_queues() 130 struct hw_eq *eq = kzalloc(sizeof(*eq), GFP_KERNEL); in efct_hw_new_eq() local 132 if (!eq) in efct_hw_new_eq() 139 eq->queue = &hw->eq[eq->instance]; in efct_hw_new_eq() 150 hw->hw_eq[eq->instance] = eq; in efct_hw_new_eq() 154 eq->queue->id, eq->entry_count); in efct_hw_new_eq() 155 return eq; in efct_hw_new_eq() 167 cq->eq = eq; in efct_hw_new_cq() 178 eq->instance, eq->entry_count); in efct_hw_new_cq() 393 if (!eq) in efct_hw_del_eq() [all …]
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/openbmc/linux/arch/powerpc/kernel/ |
H A D | cpu_setup_6xx.S | 217 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 218 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq 371 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 373 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq 374 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq 375 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq 376 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq 377 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq 442 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq 444 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq [all …]
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/openbmc/linux/drivers/pci/controller/ |
H A D | pcie-iproc-msi.c | 64 unsigned int eq; member 130 unsigned int eq) in iproc_msi_read_reg() argument 139 int eq, u32 val) in iproc_msi_write_reg() argument 334 eq = grp->eq; in iproc_msi_handler() 387 int i, eq; in iproc_msi_enable() local 410 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_enable() 422 val |= BIT(eq); in iproc_msi_enable() 430 u32 eq, val; in iproc_msi_disable() local 432 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_disable() 435 val &= ~BIT(eq); in iproc_msi_disable() [all …]
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/openbmc/linux/include/linux/mlx5/ |
H A D | eq.h | 24 mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 25 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 27 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 30 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc); 31 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm); 41 static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) in mlx5_eq_update_cc() argument 44 mlx5_eq_update_ci(eq, cc, 0); in mlx5_eq_update_cc()
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