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Searched refs:env (Results 1 – 25 of 1855) sorted by relevance

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/openbmc/qemu/linux-user/xtensa/
H A Dcpu_loop.c29 env->pc = env->sregs[EPC1]; in xtensa_rfw()
46 put_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_overflow4()
47 put_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_overflow4()
48 put_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_overflow4()
49 put_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_overflow4()
55 get_user_ual(env->regs[0], env->regs[5] - 16); in xtensa_underflow4()
56 get_user_ual(env->regs[1], env->regs[5] - 12); in xtensa_underflow4()
57 get_user_ual(env->regs[2], env->regs[5] - 8); in xtensa_underflow4()
58 get_user_ual(env->regs[3], env->regs[5] - 4); in xtensa_underflow4()
64 put_user_ual(env->regs[0], env->regs[9] - 16); in xtensa_overflow8()
[all …]
/openbmc/qemu/target/sparc/
H A Dwin_helper.c42 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
43 memcpy32(env->regbase, env->regbase + env->nwindows * 16); in cpu_set_cwp()
49 memcpy32(env->regbase + env->nwindows * 16, env->regbase); in cpu_set_cwp()
144 cwp = cpu_cwp_inc(env, env->cwp + 1) ; in helper_rett()
149 env->psrs = env->psrps; in helper_rett()
158 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save()
169 cwp = cpu_cwp_inc(env, env->cwp + 1); in helper_restore()
200 cwp = cpu_cwp_dec(env, env->cwp - 1); in helper_save()
361 dst = get_gl_gregset(env, env->gl); in cpu_gl_switch_gregs()
444 env->hpstate = env->htstate[env->tl]; in helper_done()
[all …]
H A Dint64_helper.c134 CPUSPARCState *env = &cpu->env; in sparc_cpu_do_interrupt() local
179 if (env->tl >= env->maxtl) { in sparc_cpu_do_interrupt()
185 if (env->tl < env->maxtl - 1) { in sparc_cpu_do_interrupt()
189 if (env->tl < env->maxtl) { in sparc_cpu_do_interrupt()
201 env->htstate[env->tl] = env->hpstate; in sparc_cpu_do_interrupt()
242 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); in sparc_cpu_do_interrupt()
244 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in sparc_cpu_do_interrupt()
246 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); in sparc_cpu_do_interrupt()
252 env->pc = env->tbr & ~0x7fffULL; in sparc_cpu_do_interrupt()
255 env->npc = env->pc + 4; in sparc_cpu_do_interrupt()
[all …]
/openbmc/qemu/target/i386/
H A Dhelper.h5 DEF_HELPER_1(read_eflags, tl, env)
6 DEF_HELPER_2(divb_AL, void, env, tl)
27 DEF_HELPER_1(aaa, void, env)
28 DEF_HELPER_1(aas, void, env)
29 DEF_HELPER_1(daa, void, env)
30 DEF_HELPER_1(das, void, env)
32 DEF_HELPER_2(lsl, tl, env, tl)
33 DEF_HELPER_2(lar, tl, env, tl)
45 DEF_HELPER_1(clts, void, env)
63 DEF_HELPER_1(rsm, void, env)
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/openbmc/qemu/target/i386/tcg/sysemu/
H A Dsvm_helper.c102 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state()
107 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state()
112 if ((env->efer & MSR_EFER_LME) && (env->cr[0] & CR0_PG_MASK) in is_efer_invalid_state()
238 env->intercept_cr_read = x86_lduw_phys(cs, env->vm_vmcb + in helper_vmrun()
244 env->intercept_dr_read = x86_lduw_phys(cs, env->vm_vmcb + in helper_vmrun()
297 env->tsc_offset = x86_ldq_phys(cs, env->vm_vmcb + in helper_vmrun()
428 env->exception_next_eip = env->eip; in helper_vmrun()
447 env->exception_next_eip = env->eip; in helper_vmrun()
511 svm_canonicalization(env, &env->kernelgsbase); in helper_vmload()
860 env->regs[R_ESP] = x86_ldq_phys(cs, env->vm_hsave + in do_vmexit()
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H A Dmisc_helper.c186 cpu_load_efer(env, (env->efer & ~update_mask) | in helper_wrmsr()
237 env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_wrmsr()
248 env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_wrmsr()
252 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr()
257 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr()
268 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_wrmsr()
389 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr()
400 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr()
408 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr()
419 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr()
[all …]
/openbmc/qemu/target/rx/
H A Dop_helper.c40 env->isp = env->regs[0]; in _set_psw()
41 env->regs[0] = env->usp; in _set_psw()
43 env->usp = env->regs[0]; in _set_psw()
44 env->regs[0] = env->isp; in _set_psw()
83 env->fpsw = FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); in update_fpsw()
161 env->psw_s = env->psw_o = 0; in FLOATOP()
241 cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); in helper_sstr()
300 env->psw_z = tmp - env->regs[2]; in helper_suntil()
301 env->psw_c = (tmp <= env->regs[2]); in helper_suntil()
319 env->psw_z = env->regs[3]; in helper_swhile()
[all …]
H A Dhelper.c49 CPURXState *env = &cpu->env; in rx_cpu_do_interrupt() local
56 env->usp = env->regs[0]; in rx_cpu_do_interrupt()
58 env->isp = env->regs[0]; in rx_cpu_do_interrupt()
61 env->psw_pm = env->psw_i = env->psw_u = 0; in rx_cpu_do_interrupt()
65 env->bpc = env->pc; in rx_cpu_do_interrupt()
67 env->pc = env->fintv; in rx_cpu_do_interrupt()
76 cpu_stl_data(env, env->isp, env->pc); in rx_cpu_do_interrupt()
77 env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4); in rx_cpu_do_interrupt()
91 cpu_stl_data(env, env->isp, env->pc); in rx_cpu_do_interrupt()
120 env->regs[0] = env->isp; in rx_cpu_do_interrupt()
[all …]
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
426 return env->CP0_MAAR[env->CP0_MAARI] >> 32; in helper_mfhc0_maar()
504 return env->CP0_MAAR[env->CP0_MAARI]; in helper_dmfc0_maar()
1335 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | in helper_mtc0_config4()
1341 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | in helper_mtc0_config5()
1360 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env); in helper_mtc0_maar()
1365 env->CP0_MAAR[env->CP0_MAARI] = in helper_mthc0_maar()
1643 if (&other_cpu->env != env) { in helper_dvpe()
1659 if (&other_cpu->env != env in helper_evpe()
[all …]
H A Dtlb_helper.c274 env->tlb->helper_tlbwi(env); in helper_tlbwi()
279 env->tlb->helper_tlbwr(env); in helper_tlbwr()
284 env->tlb->helper_tlbp(env); in helper_tlbp()
289 env->tlb->helper_tlbr(env); in helper_tlbr()
294 env->tlb->helper_tlbinv(env); in helper_tlbinv()
299 env->tlb->helper_tlbinvf(env); in helper_tlbinvf()
565 env->CP0_EntryHi &= env->SEGMask; in raise_mmu_exception()
914 CPUMIPSState *env = &cpu->env; in mips_cpu_tlb_fill() local
1026 env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); in set_badinstr_registers()
1037 CPUMIPSState *env = &cpu->env; in mips_cpu_do_interrupt() local
[all …]
/openbmc/qemu/linux-user/sparc/
H A Dcpu_loop.c68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & in save_window()
70 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2)); in save_window()
77 save_window_offset(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); in save_window()
92 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) & in restore_window()
97 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in restore_window()
114 if (env->cleanwin < env->nwindows - 1) in restore_window()
142 cwp1 = cpu_cwp_inc(env, env->cwp + 1); in flush_windows()
154 env->pc = env->npc; in next_instruction()
155 env->npc = env->npc + 4; in next_instruction()
243 env->pc = env->npc; in cpu_loop()
[all …]
/openbmc/qemu/target/mips/
H A Dcpu.c84 CPUMIPSState *env = &cpu->env; in mips_cpu_dump_state() local
91 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state()
105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state()
108 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); in mips_cpu_dump_state()
141 CPUMIPSState *env = &cpu->env; in mips_cpu_has_work() local
192 CPUMIPSState *env = &cpu->env; in mips_cpu_reset_hold() local
432 CPUMIPSState *env = &cpu->env; in mips_cpu_disas_set_info() local
452 CPUMIPSState *env = &cpu->env; in mips_cp0_period_set() local
463 CPUMIPSState *env = &cpu->env; in mips_cpu_realizefn() local
490 mmu_init(env, env->cpu_model); in mips_cpu_realizefn()
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H A Dinternal.h210 void msa_reset(CPUMIPSState *env);
223 env->hflags |= MIPS_HFLAG_M16; in mips_env_set_pc()
232 env->PAMask = (1ULL << env->PABITS) - 1; in restore_pamask()
234 env->PAMask = PAMASK_BASE; in restore_pamask()
283 if ((&other_cpu->env != env) && in mips_vp_active()
299 env->hflags |= MIPS_HFLAG_ERL; in compute_hflags()
304 env->hflags |= (env->CP0_Status >> CP0St_KSU) & in compute_hflags()
312 env->hflags |= MIPS_HFLAG_64; in compute_hflags()
333 env->hflags |= MIPS_HFLAG_CP0; in compute_hflags()
336 env->hflags |= MIPS_HFLAG_FPU; in compute_hflags()
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/openbmc/qemu/target/riscv/
H A Dfpu_helper.c222 return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); in helper_fadd_s()
229 return nanbox_s(env, float32_sub(frs1, frs2, &env->fp_status)); in helper_fsub_s()
236 return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); in helper_fmul_s()
243 return nanbox_s(env, float32_div(frs1, frs2, &env->fp_status)); in helper_fdiv_s()
250 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_s()
267 return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_s()
283 return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); in helper_fsqrt_s()
357 return nanbox_s(env, int64_to_float32(rs1, &env->fp_status)); in helper_fcvt_s_l()
583 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmin_h()
600 return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? in helper_fmax_h()
[all …]
H A Dcpu_helper.c72 *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc; in cpu_get_tb_cpu_state()
406 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()
415 uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; in riscv_cpu_vsirq_pending()
458 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()
468 irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie; in riscv_cpu_local_irq_pending()
559 env->vsepc = env->sepc; in riscv_cpu_swap_hypervisor_regs()
568 env->vsatp = env->satp; in riscv_cpu_swap_hypervisor_regs()
663 irqf = env->hvien & env->hvip & env->vsie; in riscv_cpu_interrupt()
665 irqf = env->mvien & env->mvip & env->sie; in riscv_cpu_interrupt()
1781 env->sepc = env->pc; in riscv_cpu_do_interrupt()
[all …]
/openbmc/qemu/target/xtensa/
H A Dexc_helper.c81 HELPER(debug_exception)(env, env->pc, cause); in debug_exception_env()
92 env->sregs[EPS2 + level - 2] = env->sregs[PS]; in HELPER()
105 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | in HELPER()
176 env->sregs[EPC1 + level - 1] = env->pc; in handle_interrupt()
180 env->pc = relocated_vector(env, in handle_interrupt()
190 env->sregs[DEPC] = env->pc; in handle_interrupt()
192 env->sregs[EPC1] = env->pc; in handle_interrupt()
196 env->sregs[EPC1] = env->pc; in handle_interrupt()
209 CPUXtensaState *env = &cpu->env; in xtensa_cpu_do_interrupt() local
219 env->pc, env->regs[0], env->sregs[PS], in xtensa_cpu_do_interrupt()
[all …]
H A Dwin_helper.c40 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
44 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
46 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys()
56 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window()
60 memcpy(env->phys_regs + phys, env->regs + window, in copy_phys_from_window()
62 memcpy(env->phys_regs, env->regs + window + n1, in copy_phys_from_window()
110 env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env); in HELPER()
123 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER()
125 env->sregs[EPC1] = env->pc = pc; in HELPER()
173 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) | in HELPER()
[all …]
/openbmc/qemu/target/sh4/
H A Dop_helper.c34 env->tea = addr; in superh_cpu_do_unaligned_access()
56 cpu_load_tlb(env); in helper_ldtlb()
64 CPUState *cs = env_cpu(env); in raise_exception()
95 env->in_sleep = 1; in helper_sleep()
101 env->tra = tra << 2; in helper_trapa()
136 env->movcal_backup_tail = &(env->movcal_backup); in helper_discard_movcal_backup()
167 res = ((uint64_t) env->mach << 32) | env->macl; in helper_macl()
183 res = ((uint64_t) env->mach << 32) | env->macl; in helper_macw()
189 env->mach = 1; in helper_macw()
192 env->mach = 1; in helper_macw()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c216 CPUARMState *env = &cpu->env; in v7m_stack_write() local
304 CPUARMState *env = &cpu->env; in v7m_stack_read() local
659 CPUARMState *env = &cpu->env; in arm_v7m_load_vector() local
763 CPUARMState *env = &cpu->env; in v7m_push_callee_stack() local
840 CPUARMState *env = &cpu->env; in v7m_exception_taken() local
1184 CPUARMState *env = &cpu->env; in v7m_push_stack() local
1358 CPUARMState *env = &cpu->env; in do_v7m_exception_exit() local
1916 CPUARMState *env = &cpu->env; in do_v7m_function_return() local
1993 CPUARMState *env = &cpu->env; in v7m_read_half_insn() local
2041 CPUARMState *env = &cpu->env; in v7m_read_sg_stack_word() local
[all …]
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
32 DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32)
33 DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32)
217 DEF_HELPER_FLAGS_1(mve_vpnot, TCG_CALL_NO_WG, void, env)
[all …]
/openbmc/qemu/target/hppa/
H A Dgdbstub.c40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
115 val = env->cr[24]; in hppa_cpu_gdb_read_register()
118 val = env->cr[25]; in hppa_cpu_gdb_read_register()
121 val = env->cr[26]; in hppa_cpu_gdb_read_register()
124 val = env->cr[27]; in hppa_cpu_gdb_read_register()
127 val = env->cr[28]; in hppa_cpu_gdb_read_register()
160 env->gr[n] = val; in hppa_cpu_gdb_write_register()
163 env->cr[CR_SAR] = val & (hppa_is_pa20(env) ? 63 : 31); in hppa_cpu_gdb_write_register()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dsysemu_helper.h.inc18 DEF_HELPER_1(mfc0_random, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
34 DEF_HELPER_1(mfc0_saar, tl, env)
39 DEF_HELPER_1(mftc0_epc, tl, env)
153 DEF_HELPER_1(mftdsp, tl, env)
161 DEF_HELPER_1(dvpe, tl, env)
162 DEF_HELPER_1(evpe, tl, env)
165 DEF_HELPER_1(dvp, tl, env)
166 DEF_HELPER_1(evp, tl, env)
178 DEF_HELPER_1(di, tl, env)
[all …]
H A Dfpu_helper.c98 compute_hflags(env); in helper_ctc1()
110 compute_hflags(env); in helper_ctc1()
122 compute_hflags(env); in helper_ctc1()
134 compute_hflags(env); in helper_ctc1()
143 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | in helper_ctc1()
151 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | in helper_ctc1()
158 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | in helper_ctc1()
163 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) | in helper_ctc1()
164 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask)); in helper_ctc1()
172 restore_fp_status(env); in helper_ctc1()
[all …]
/openbmc/qemu/target/ppc/
H A Dexcp_helper.c291 CPUPPCState *env = &cpu->env; in ppc_excp_apply_ail() local
388 CPUPPCState *env = &cpu->env; in powerpc_reset_excp_state() local
398 CPUPPCState *env = &cpu->env; in powerpc_set_excp_state() local
449 CPUPPCState *env = &cpu->env; in powerpc_excp_40x() local
562 env->spr[srr0] = env->nip; in powerpc_excp_40x()
1255 env->spr[srr0] = env->nip; in powerpc_excp_booke()
1368 return is_prefix_insn(env, ppc_ldl_code(env, env->nip)); in is_prefix_insn_excp()
1560 env->lr = env->nip; in powerpc_excp_books()
2759 do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); in helper_rfid()
2764 do_rfi(env, env->lr, env->ctr); in helper_rfscv()
[all …]
/openbmc/linux/drivers/iio/adc/
H A Denvelope-detector.c85 env->comp = 0; in envelope_detector_comp_latch()
141 env->level = (env->high + env->low + !env->invert) / 2; in envelope_detector_setup_compare()
143 if (env->high == env->low + 1) { in envelope_detector_setup_compare()
149 ret = iio_write_channel_raw(env->dac, env->invert ? 0 : env->dac_max); in envelope_detector_setup_compare()
157 ret = iio_write_channel_raw(env->dac, env->level); in envelope_detector_setup_compare()
177 if (!envelope_detector_comp_latch(env) ^ !env->invert) in envelope_detector_timeout()
178 env->low = env->level; in envelope_detector_timeout()
180 env->high = env->level; in envelope_detector_timeout()
206 env->high = env->dac_max + env->invert; in envelope_detector_read_raw()
207 env->low = -1 + env->invert; in envelope_detector_read_raw()
[all …]

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