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Searched refs:env (Results 1 – 25 of 1638) sorted by relevance

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/openbmc/qemu/linux-user/xtensa/
H A Dcpu_loop.c26 static void xtensa_rfw(CPUXtensaState *env) in xtensa_rfw() argument
28 xtensa_restore_owb(env); in xtensa_rfw()
29 env->pc = env->sregs[EPC1]; in xtensa_rfw()
32 static void xtensa_rfwu(CPUXtensaState *env) in xtensa_rfwu() argument
34 env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]); in xtensa_rfwu()
35 xtensa_rfw(env); in xtensa_rfwu()
38 static void xtensa_rfwo(CPUXtensaState *env) in xtensa_rfwo() argument
40 env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]); in xtensa_rfwo()
41 xtensa_rfw(env); in xtensa_rfwo()
44 static void xtensa_overflow4(CPUXtensaState *env) in xtensa_overflow4() argument
[all …]
/openbmc/qemu/target/sparc/
H A Dwin_helper.c26 void cpu_set_cwp(CPUSPARCState *env, int new_cwp) in cpu_set_cwp() argument
29 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
30 memcpy(env->regbase, env->regbase + env->nwindows * 16, in cpu_set_cwp()
31 sizeof(env->gregs)); in cpu_set_cwp()
33 env->cwp = new_cwp; in cpu_set_cwp()
36 if (new_cwp == env->nwindows - 1) { in cpu_set_cwp()
37 memcpy(env->regbase + env->nwindows * 16, env->regbase, in cpu_set_cwp()
38 sizeof(env->gregs)); in cpu_set_cwp()
40 env->regwptr = env->regbase + (new_cwp * 16); in cpu_set_cwp()
43 target_ulong cpu_get_psr(CPUSPARCState *env) in cpu_get_psr() argument
[all …]
H A Dint64_helper.c65 void cpu_check_irqs(CPUSPARCState *env) in cpu_check_irqs() argument
68 uint32_t pil = env->pil_in | in cpu_check_irqs()
69 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); in cpu_check_irqs()
75 if (env->ivec_status & 0x20) { in cpu_check_irqs()
78 cs = env_cpu(env); in cpu_check_irqs()
83 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { in cpu_check_irqs()
91 if (pil < (2 << env->psrpil)) { in cpu_check_irqs()
93 trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); in cpu_check_irqs()
94 env->interrupt_index = 0; in cpu_check_irqs()
100 if (cpu_interrupts_enabled(env)) { in cpu_check_irqs()
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/openbmc/qemu/target/i386/
H A Dhelper.h5 DEF_HELPER_3(write_eflags, void, env, tl, i32)
6 DEF_HELPER_1(read_eflags, tl, env)
7 DEF_HELPER_2(divb_AL, void, env, tl)
8 DEF_HELPER_2(idivb_AL, void, env, tl)
9 DEF_HELPER_2(divw_AX, void, env, tl)
10 DEF_HELPER_2(idivw_AX, void, env, tl)
11 DEF_HELPER_2(divl_EAX, void, env, tl)
12 DEF_HELPER_2(idivl_EAX, void, env, tl)
14 DEF_HELPER_2(divq_EAX, void, env, tl)
15 DEF_HELPER_2(idivq_EAX, void, env, tl)
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/openbmc/qemu/target/i386/tcg/system/
H A Dsvm_helper.c30 static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_save_seg() argument
33 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_save_seg()
35 cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_save_seg()
37 cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
39 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), in svm_save_seg()
49 static inline void svm_canonicalization(CPUX86State *env, target_ulong *seg_base) in svm_canonicalization() argument
51 uint16_t shift_amt = 64 - cpu_x86_virtual_addr_width(env); in svm_canonicalization()
55 static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_load_seg() argument
61 cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_load_seg()
64 cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_load_seg()
[all …]
H A Dmisc_helper.c31 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) in helper_outb() argument
34 cpu_get_mem_attrs(env), NULL); in helper_outb()
37 target_ulong helper_inb(CPUX86State *env, uint32_t port) in helper_inb() argument
40 cpu_get_mem_attrs(env), NULL); in helper_inb()
43 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) in helper_outw() argument
46 cpu_get_mem_attrs(env), NULL); in helper_outw()
49 target_ulong helper_inw(CPUX86State *env, uint32_t port) in helper_inw() argument
52 cpu_get_mem_attrs(env), NULL); in helper_inw()
55 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) in helper_outl() argument
58 cpu_get_mem_attrs(env), NULL); in helper_outl()
[all …]
/openbmc/qemu/target/rx/
H A Dop_helper.c28 void raise_exception(CPURXState *env, int index,
31 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) in _set_psw() argument
34 prev_u = env->psw_u; in _set_psw()
35 rx_cpu_unpack_psw(env, psw, rte); in _set_psw()
36 if (prev_u != env->psw_u) { in _set_psw()
38 if (env->psw_u) { in _set_psw()
39 env->isp = env->regs[0]; in _set_psw()
40 env->regs[0] = env->usp; in _set_psw()
42 env->usp = env->regs[0]; in _set_psw()
43 env->regs[0] = env->isp; in _set_psw()
[all …]
H A Dhelper.c26 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) in rx_cpu_unpack_psw() argument
28 if (env->psw_pm == 0) { in rx_cpu_unpack_psw()
29 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); in rx_cpu_unpack_psw()
32 env->psw_pm = FIELD_EX32(psw, PSW, PM); in rx_cpu_unpack_psw()
34 env->psw_u = FIELD_EX32(psw, PSW, U); in rx_cpu_unpack_psw()
35 env->psw_i = FIELD_EX32(psw, PSW, I); in rx_cpu_unpack_psw()
37 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; in rx_cpu_unpack_psw()
38 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; in rx_cpu_unpack_psw()
39 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); in rx_cpu_unpack_psw()
40 env->psw_c = FIELD_EX32(psw, PSW, C); in rx_cpu_unpack_psw()
[all …]
/openbmc/qemu/target/riscv/
H A Dop_helper.c32 G_NORETURN void riscv_raise_exception(CPURISCVState *env, in riscv_raise_exception() argument
36 CPUState *cs = env_cpu(env); in riscv_raise_exception()
40 env->pc); in riscv_raise_exception()
46 void helper_raise_exception(CPURISCVState *env, uint32_t exception) in helper_raise_exception() argument
48 riscv_raise_exception(env, exception, 0); in helper_raise_exception()
51 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr() argument
59 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_csrr()
63 RISCVException ret = riscv_csrr(env, csr, &val); in helper_csrr()
66 riscv_raise_exception(env, ret, GETPC()); in helper_csrr()
71 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) in helper_csrw() argument
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H A Dfpu_helper.c26 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags() argument
28 int soft = get_float_exception_flags(&env->fp_status); in riscv_cpu_get_fflags()
40 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags() argument
50 set_float_exception_flags(soft, &env->fp_status); in riscv_cpu_set_fflags()
53 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode() argument
58 rm = env->frm; in helper_set_rounding_mode()
77 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_set_rounding_mode()
80 set_float_rounding_mode(softrm, &env->fp_status); in helper_set_rounding_mode()
83 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode_chkfrm() argument
88 if (unlikely(env->frm >= 5)) { in helper_set_rounding_mode_chkfrm()
[all …]
H A Dcpu_helper.c40 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) in riscv_env_mmu_index() argument
45 bool virt = env->virt_enabled; in riscv_env_mmu_index()
46 int mode = env->priv; in riscv_env_mmu_index()
50 uint64_t status = env->mstatus; in riscv_env_mmu_index()
53 mode = get_field(env->mstatus, MSTATUS_MPP); in riscv_env_mmu_index()
54 virt = get_field(env->mstatus, MSTATUS_MPV) && in riscv_env_mmu_index()
57 status = env->vsstatus; in riscv_env_mmu_index()
69 bool cpu_get_fcfien(CPURISCVState *env) in cpu_get_fcfien() argument
72 if (!env_archcpu(env)->cfg.ext_zicfilp) { in cpu_get_fcfien()
76 switch (env->priv) { in cpu_get_fcfien()
[all …]
/openbmc/qemu/linux-user/sparc/
H A Dcpu_loop.c32 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) in get_reg_index() argument
34 index = (index + cwp * 16) % (16 * env->nwindows); in get_reg_index()
37 if (index < 8 && env->cwp == env->nwindows - 1) in get_reg_index()
38 index += 16 * env->nwindows; in get_reg_index()
43 static inline void save_window_offset(CPUSPARCState *env, int cwp1) in save_window_offset() argument
48 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; in save_window_offset()
59 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); in save_window_offset()
64 static void save_window(CPUSPARCState *env) in save_window() argument
68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & in save_window()
69 ((1LL << env->nwindows) - 1); in save_window()
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/openbmc/qemu/target/hppa/
H A Dgdbstub.c32 CPUHPPAState *env = cpu_env(cs); in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
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/openbmc/qemu/target/xtensa/
H A Dwin_helper.c34 static void copy_window_from_phys(CPUXtensaState *env, in copy_window_from_phys() argument
37 assert(phys < env->config->nareg); in copy_window_from_phys()
38 if (phys + n <= env->config->nareg) { in copy_window_from_phys()
39 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
42 uint32_t n1 = env->config->nareg - phys; in copy_window_from_phys()
43 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
45 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys()
50 static void copy_phys_from_window(CPUXtensaState *env, in copy_phys_from_window() argument
53 assert(phys < env->config->nareg); in copy_phys_from_window()
54 if (phys + n <= env->config->nareg) { in copy_phys_from_window()
[all …]
H A Dexc_helper.c36 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) in HELPER()
38 CPUState *cs = env_cpu(env); in HELPER()
42 env->yield_needed = 0; in HELPER()
47 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
51 env->pc = pc; in HELPER()
52 if (env->sregs[PS] & PS_EXCM) { in HELPER()
53 if (env->config->ndepc) { in HELPER()
54 env->sregs[DEPC] = pc; in HELPER()
56 env->sregs[EPC1] = pc; in HELPER()
60 env->sregs[EPC1] = pc; in HELPER()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dsystem_helper.h.inc13 DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
14 DEF_HELPER_1(mfc0_mvpconf0, tl, env)
15 DEF_HELPER_1(mfc0_mvpconf1, tl, env)
16 DEF_HELPER_1(mftc0_vpecontrol, tl, env)
17 DEF_HELPER_1(mftc0_vpeconf0, tl, env)
18 DEF_HELPER_1(mfc0_random, tl, env)
19 DEF_HELPER_1(mfc0_tcstatus, tl, env)
20 DEF_HELPER_1(mftc0_tcstatus, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
22 DEF_HELPER_1(mftc0_tcbind, tl, env)
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/openbmc/qemu/target/mips/
H A Dcpu.c67 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) in fpu_dump_state() argument
70 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); in fpu_dump_state()
74 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, in fpu_dump_state()
75 get_float_exception_flags(&env->active_fpu.fp_status)); in fpu_dump_state()
78 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); in fpu_dump_state()
84 CPUMIPSState *env = cpu_env(cs); in mips_cpu_dump_state() local
90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], in mips_cpu_dump_state()
91 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state()
97 regnames[i], env->active_tc.gpr[i]); in mips_cpu_dump_state()
105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state()
[all …]
/openbmc/qemu/target/mips/tcg/system/
H A Dcp0_helper.c38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
44 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
52 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
81 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
91 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
113 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
121 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
123 *tc = env->current_tc; in mips_cpu_map_tc()
124 return env; in mips_cpu_map_tc()
[all …]
H A Dtlb_helper.c32 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) in r4k_mips_tlb_flush_extra() argument
35 while (env->tlb->tlb_in_use > first) { in r4k_mips_tlb_flush_extra()
36 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
50 static void r4k_fill_tlb(CPUMIPSState *env, int idx) in r4k_fill_tlb() argument
53 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); in r4k_fill_tlb()
56 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
57 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { in r4k_fill_tlb()
62 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); in r4k_fill_tlb()
64 tlb->VPN &= env->SEGMask; in r4k_fill_tlb()
66 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; in r4k_fill_tlb()
[all …]
H A Dspecial_helper.c29 target_ulong helper_di(CPUMIPSState *env) in helper_di() argument
31 target_ulong t0 = env->CP0_Status; in helper_di()
33 env->CP0_Status = t0 & ~(1 << CP0St_IE); in helper_di()
37 target_ulong helper_ei(CPUMIPSState *env) in helper_ei() argument
39 target_ulong t0 = env->CP0_Status; in helper_ei()
41 env->CP0_Status = t0 | (1 << CP0St_IE); in helper_ei()
45 static void debug_pre_eret(CPUMIPSState *env) in debug_pre_eret() argument
49 env->active_tc.PC, env->CP0_EPC); in debug_pre_eret()
50 if (env->CP0_Status & (1 << CP0St_ERL)) { in debug_pre_eret()
51 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); in debug_pre_eret()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c27 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, in v7m_msr_xpsr() argument
37 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { in v7m_msr_xpsr()
40 xpsr_write(env, val, apsrmask); in v7m_msr_xpsr()
44 static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) in v7m_mrs_xpsr() argument
53 if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { in v7m_mrs_xpsr()
58 return xpsr_read(env) & mask; in v7m_mrs_xpsr()
61 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) in arm_v7m_mrs_control() argument
63 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
67 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()
74 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) in HELPER()
[all …]
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
27 DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
28 DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32)
29 DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
[all …]
/openbmc/qemu/target/sh4/
H A Dop_helper.c48 void helper_ldtlb(CPUSH4State *env) in helper_ldtlb() argument
51 cpu_abort(env_cpu(env), "Unhandled ldtlb"); in helper_ldtlb()
53 cpu_load_tlb(env); in helper_ldtlb()
58 void raise_exception(CPUSH4State *env, int index, in raise_exception() argument
61 CPUState *cs = env_cpu(env); in raise_exception()
67 void helper_raise_illegal_instruction(CPUSH4State *env) in helper_raise_illegal_instruction() argument
69 raise_exception(env, 0x180, 0); in helper_raise_illegal_instruction()
72 void helper_raise_slot_illegal_instruction(CPUSH4State *env) in helper_raise_slot_illegal_instruction() argument
74 raise_exception(env, 0x1a0, 0); in helper_raise_slot_illegal_instruction()
77 void helper_raise_fpu_disable(CPUSH4State *env) in helper_raise_fpu_disable() argument
[all …]
/openbmc/qemu/target/mips/system/
H A Dcp0_timer.c30 static uint32_t cpu_mips_get_count_val(CPUMIPSState *env) in cpu_mips_get_count_val() argument
34 return env->CP0_Count + in cpu_mips_get_count_val()
35 (uint32_t)clock_ns_to_ticks(env->count_clock, now_ns); in cpu_mips_get_count_val()
38 static void cpu_mips_timer_update(CPUMIPSState *env) in cpu_mips_timer_update() argument
44 wait = env->CP0_Compare - cpu_mips_get_count_val(env); in cpu_mips_timer_update()
49 next_ns = now_ns + clock_ticks_to_ns(env->count_clock, wait); in cpu_mips_timer_update()
50 timer_mod(env->timer, next_ns); in cpu_mips_timer_update()
54 static void cpu_mips_timer_expire(CPUMIPSState *env) in cpu_mips_timer_expire() argument
56 cpu_mips_timer_update(env); in cpu_mips_timer_expire()
57 if (env->insn_flags & ISA_MIPS_R2) { in cpu_mips_timer_expire()
[all …]
/openbmc/qemu/hw/xtensa/
H A Dpic_cpu.c36 void check_interrupts(CPUXtensaState *env) in check_interrupts() argument
38 CPUState *cs = env_cpu(env); in check_interrupts()
39 int minlevel = xtensa_get_cintlevel(env); in check_interrupts()
40 uint32_t int_set_enabled = env->sregs[INTSET] & in check_interrupts()
41 (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]); in check_interrupts()
44 if (minlevel >= env->config->nmi_level) { in check_interrupts()
45 minlevel = env->config->nmi_level - 1; in check_interrupts()
47 for (level = env->config->nlevel; level > minlevel; --level) { in check_interrupts()
48 if (env->config->level_mask[level] & int_set_enabled) { in check_interrupts()
49 env->pending_irq_level = level; in check_interrupts()
[all …]

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