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Searched refs:env (Results 1 – 25 of 1973) sorted by relevance

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/openbmc/qemu/linux-user/xtensa/
H A Dcpu_loop.c26 static void xtensa_rfw(CPUXtensaState *env) in xtensa_rfw() argument
28 xtensa_restore_owb(env); in xtensa_rfw()
29 env->pc = env->sregs[EPC1]; in xtensa_rfw()
32 static void xtensa_rfwu(CPUXtensaState *env) in xtensa_rfwu() argument
34 env->sregs[WINDOW_START] |= (1 << env->sregs[WINDOW_BASE]); in xtensa_rfwu()
35 xtensa_rfw(env); in xtensa_rfwu()
38 static void xtensa_rfwo(CPUXtensaState *env) in xtensa_rfwo() argument
40 env->sregs[WINDOW_START] &= ~(1 << env->sregs[WINDOW_BASE]); in xtensa_rfwo()
41 xtensa_rfw(env); in xtensa_rfwo()
44 static void xtensa_overflow4(CPUXtensaState *env) in xtensa_overflow4() argument
[all …]
/openbmc/qemu/target/sparc/
H A Dwin_helper.c39 void cpu_set_cwp(CPUSPARCState *env, int new_cwp) in cpu_set_cwp() argument
42 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
43 memcpy32(env->regbase, env->regbase + env->nwindows * 16); in cpu_set_cwp()
45 env->cwp = new_cwp; in cpu_set_cwp()
48 if (new_cwp == env->nwindows - 1) { in cpu_set_cwp()
49 memcpy32(env->regbase + env->nwindows * 16, env->regbase); in cpu_set_cwp()
51 env->regwptr = env->regbase + (new_cwp * 16); in cpu_set_cwp()
54 target_ulong cpu_get_psr(CPUSPARCState *env) in cpu_get_psr() argument
58 icc |= ((int32_t)env->cc_N < 0) << PSR_NEG_SHIFT; in cpu_get_psr()
59 icc |= ((int32_t)env->cc_V < 0) << PSR_OVF_SHIFT; in cpu_get_psr()
[all …]
H A Dint64_helper.c65 void cpu_check_irqs(CPUSPARCState *env) in cpu_check_irqs() argument
68 uint32_t pil = env->pil_in | in cpu_check_irqs()
69 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); in cpu_check_irqs()
75 if (env->ivec_status & 0x20) { in cpu_check_irqs()
78 cs = env_cpu(env); in cpu_check_irqs()
83 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { in cpu_check_irqs()
91 if (pil < (2 << env->psrpil)) { in cpu_check_irqs()
93 trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); in cpu_check_irqs()
94 env->interrupt_index = 0; in cpu_check_irqs()
100 if (cpu_interrupts_enabled(env)) { in cpu_check_irqs()
[all …]
/openbmc/qemu/target/i386/
H A Dhelper.h5 DEF_HELPER_3(write_eflags, void, env, tl, i32)
6 DEF_HELPER_1(read_eflags, tl, env)
7 DEF_HELPER_2(divb_AL, void, env, tl)
8 DEF_HELPER_2(idivb_AL, void, env, tl)
9 DEF_HELPER_2(divw_AX, void, env, tl)
10 DEF_HELPER_2(idivw_AX, void, env, tl)
11 DEF_HELPER_2(divl_EAX, void, env, tl)
12 DEF_HELPER_2(idivl_EAX, void, env, tl)
14 DEF_HELPER_2(divq_EAX, void, env, tl)
15 DEF_HELPER_2(idivq_EAX, void, env, tl)
[all …]
H A Dmachine.c222 CPUX86State *env = &cpu->env; in cpu_pre_save() local
224 env->v_tpr = env->int_ctl & V_TPR_MASK; in cpu_pre_save()
226 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; in cpu_pre_save()
227 env->fptag_vmstate = 0; in cpu_pre_save()
229 env->fptag_vmstate |= ((!env->fptags[i]) << i); in cpu_pre_save()
232 env->fpregs_format_vmstate = 0; in cpu_pre_save()
241 if (!(env->cr[0] & CR0_PE_MASK) && in cpu_pre_save()
242 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) { in cpu_pre_save()
243 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK); in cpu_pre_save()
244 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK); in cpu_pre_save()
[all …]
/openbmc/qemu/target/i386/tcg/sysemu/
H A Dsvm_helper.c30 static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_save_seg() argument
33 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_save_seg()
35 cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_save_seg()
37 cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), in svm_save_seg()
39 cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), in svm_save_seg()
49 static inline void svm_canonicalization(CPUX86State *env, target_ulong *seg_base) in svm_canonicalization() argument
51 uint16_t shift_amt = 64 - cpu_x86_virtual_addr_width(env); in svm_canonicalization()
55 static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr, in svm_load_seg() argument
61 cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), in svm_load_seg()
64 cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), in svm_load_seg()
[all …]
H A Dmisc_helper.c30 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) in helper_outb() argument
33 cpu_get_mem_attrs(env), NULL); in helper_outb()
36 target_ulong helper_inb(CPUX86State *env, uint32_t port) in helper_inb() argument
39 cpu_get_mem_attrs(env), NULL); in helper_inb()
42 void helper_outw(CPUX86State *env, uint32_t port, uint32_t data) in helper_outw() argument
45 cpu_get_mem_attrs(env), NULL); in helper_outw()
48 target_ulong helper_inw(CPUX86State *env, uint32_t port) in helper_inw() argument
51 cpu_get_mem_attrs(env), NULL); in helper_inw()
54 void helper_outl(CPUX86State *env, uint32_t port, uint32_t data) in helper_outl() argument
57 cpu_get_mem_attrs(env), NULL); in helper_outl()
[all …]
/openbmc/qemu/target/rx/
H A Dop_helper.c29 void raise_exception(CPURXState *env, int index,
32 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) in _set_psw() argument
35 prev_u = env->psw_u; in _set_psw()
36 rx_cpu_unpack_psw(env, psw, rte); in _set_psw()
37 if (prev_u != env->psw_u) { in _set_psw()
39 if (env->psw_u) { in _set_psw()
40 env->isp = env->regs[0]; in _set_psw()
41 env->regs[0] = env->usp; in _set_psw()
43 env->usp = env->regs[0]; in _set_psw()
44 env->regs[0] = env->isp; in _set_psw()
[all …]
/openbmc/qemu/target/mips/tcg/sysemu/
H A Dcp0_helper.c37 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
43 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
49 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
51 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
80 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
90 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
112 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
120 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
122 *tc = env->current_tc; in mips_cpu_map_tc()
123 return env; in mips_cpu_map_tc()
[all …]
H A Dtlb_helper.c31 static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) in r4k_mips_tlb_flush_extra() argument
34 while (env->tlb->tlb_in_use > first) { in r4k_mips_tlb_flush_extra()
35 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); in r4k_mips_tlb_flush_extra()
49 static void r4k_fill_tlb(CPUMIPSState *env, int idx) in r4k_fill_tlb() argument
52 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); in r4k_fill_tlb()
55 tlb = &env->tlb->mmu.r4k.tlb[idx]; in r4k_fill_tlb()
56 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { in r4k_fill_tlb()
61 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); in r4k_fill_tlb()
63 tlb->VPN &= env->SEGMask; in r4k_fill_tlb()
65 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; in r4k_fill_tlb()
[all …]
/openbmc/qemu/target/riscv/
H A Dfpu_helper.c27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags() argument
29 int soft = get_float_exception_flags(&env->fp_status); in riscv_cpu_get_fflags()
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags() argument
51 set_float_exception_flags(soft, &env->fp_status); in riscv_cpu_set_fflags()
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode() argument
59 rm = env->frm; in helper_set_rounding_mode()
78 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_set_rounding_mode()
81 set_float_rounding_mode(softrm, &env->fp_status); in helper_set_rounding_mode()
84 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode_chkfrm() argument
89 if (unlikely(env->frm >= 5)) { in helper_set_rounding_mode_chkfrm()
[all …]
H A Dop_helper.c29 G_NORETURN void riscv_raise_exception(CPURISCVState *env, in riscv_raise_exception() argument
32 CPUState *cs = env_cpu(env); in riscv_raise_exception()
37 void helper_raise_exception(CPURISCVState *env, uint32_t exception) in helper_raise_exception() argument
39 riscv_raise_exception(env, exception, 0); in helper_raise_exception()
42 target_ulong helper_csrr(CPURISCVState *env, int csr) in helper_csrr() argument
50 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_csrr()
54 RISCVException ret = riscv_csrr(env, csr, &val); in helper_csrr()
57 riscv_raise_exception(env, ret, GETPC()); in helper_csrr()
62 void helper_csrw(CPURISCVState *env, int csr, target_ulong src) in helper_csrw() argument
64 target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; in helper_csrw()
[all …]
H A Dcpu_helper.c39 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) in riscv_env_mmu_index()
44 bool virt = env->virt_enabled; in riscv_env_mmu_index()
45 int mode = env->priv; in riscv_env_mmu_index()
49 uint64_t status = env->mstatus; in riscv_env_mmu_index()
52 mode = get_field(env->mstatus, MSTATUS_MPP); in riscv_env_mmu_index()
53 virt = get_field(env->mstatus, MSTATUS_MPV) && in riscv_env_mmu_index()
56 status = env->vsstatus; in riscv_env_mmu_index()
68 bool cpu_get_fcfien(CPURISCVState *env) in cpu_get_fcfien()
71 if (!env_archcpu(env)->cfg.ext_zicfilp) { in cpu_get_fcfien()
75 switch (env in cpu_get_fcfien()
38 riscv_env_mmu_index(CPURISCVState * env,bool ifetch) riscv_env_mmu_index() argument
67 cpu_get_fcfien(CPURISCVState * env) cpu_get_fcfien() argument
94 cpu_get_bcfien(CPURISCVState * env) cpu_get_bcfien() argument
123 cpu_get_tb_cpu_state(CPURISCVState * env,vaddr * pc,uint64_t * cs_base,uint32_t * pflags) cpu_get_tb_cpu_state() argument
223 riscv_cpu_update_mask(CPURISCVState * env) riscv_cpu_update_mask() argument
415 riscv_cpu_pending_to_irq(CPURISCVState * env,int extirq,unsigned int extirq_def_prio,uint64_t pending,uint8_t * iprio) riscv_cpu_pending_to_irq() argument
459 riscv_cpu_all_pending(CPURISCVState * env) riscv_cpu_all_pending() argument
468 riscv_cpu_mirq_pending(CPURISCVState * env) riscv_cpu_mirq_pending() argument
477 riscv_cpu_sirq_pending(CPURISCVState * env) riscv_cpu_sirq_pending() argument
487 riscv_cpu_vsirq_pending(CPURISCVState * env) riscv_cpu_vsirq_pending() argument
502 riscv_cpu_local_irq_pending(CPURISCVState * env) riscv_cpu_local_irq_pending() argument
572 CPURISCVState *env = &cpu->env; riscv_cpu_exec_interrupt() local
584 riscv_cpu_fp_enabled(CPURISCVState * env) riscv_cpu_fp_enabled() argument
597 riscv_cpu_vector_enabled(CPURISCVState * env) riscv_cpu_vector_enabled() argument
609 riscv_cpu_swap_hypervisor_regs(CPURISCVState * env) riscv_cpu_swap_hypervisor_regs() argument
680 riscv_cpu_get_geilen(CPURISCVState * env) riscv_cpu_get_geilen() argument
689 riscv_cpu_set_geilen(CPURISCVState * env,target_ulong geilen) riscv_cpu_set_geilen() argument
704 CPURISCVState *env = &cpu->env; riscv_cpu_claim_interrupts() local
713 riscv_cpu_interrupt(CPURISCVState * env) riscv_cpu_interrupt() argument
737 riscv_cpu_update_mip(CPURISCVState * env,uint64_t mask,uint64_t value) riscv_cpu_update_mip() argument
753 riscv_cpu_set_rdtime_fn(CPURISCVState * env,uint64_t (* fn)(void *),void * arg) riscv_cpu_set_rdtime_fn() argument
760 riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState * env,uint32_t priv,int (* rmw_fn)(void * arg,target_ulong reg,target_ulong * val,target_ulong new_val,target_ulong write_mask),void * rmw_fn_arg) riscv_cpu_set_aia_ireg_rmw_fn() argument
774 riscv_cpu_set_mode(CPURISCVState * env,target_ulong newpriv,bool virt_en) riscv_cpu_set_mode() argument
836 get_physical_address_pmp(CPURISCVState * env,int * prot,hwaddr addr,int size,MMUAccessType access_type,int mode) get_physical_address_pmp() argument
882 get_physical_address(CPURISCVState * env,hwaddr * physical,int * ret_prot,vaddr addr,target_ulong * fault_pte_addr,int access_type,int mmu_idx,bool first_stage,bool two_stage,bool is_debug,bool is_probe) get_physical_address() argument
1288 raise_mmu_exception(CPURISCVState * env,target_ulong address,MMUAccessType access_type,bool pmp_violation,bool first_stage,bool two_stage,bool two_stage_indirect) raise_mmu_exception() argument
1334 CPURISCVState *env = &cpu->env; riscv_cpu_get_phys_page_debug() local
1361 CPURISCVState *env = &cpu->env; riscv_cpu_do_transaction_failed() local
1382 CPURISCVState *env = &cpu->env; riscv_cpu_do_unaligned_access() local
1437 CPURISCVState *env = &cpu->env; riscv_cpu_tlb_fill() local
1562 riscv_transformed_insn(CPURISCVState * env,target_ulong insn,target_ulong taddr) riscv_transformed_insn() argument
1792 CPURISCVState *env = &cpu->env; riscv_cpu_do_interrupt() local
[all...]
/openbmc/qemu/linux-user/sparc/
H A Dcpu_loop.c32 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index) in get_reg_index() argument
34 index = (index + cwp * 16) % (16 * env->nwindows); in get_reg_index()
37 if (index < 8 && env->cwp == env->nwindows - 1) in get_reg_index()
38 index += 16 * env->nwindows; in get_reg_index()
43 static inline void save_window_offset(CPUSPARCState *env, int cwp1) in save_window_offset() argument
48 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)]; in save_window_offset()
59 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr); in save_window_offset()
64 static void save_window(CPUSPARCState *env) in save_window() argument
68 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) & in save_window()
69 ((1LL << env->nwindows) - 1); in save_window()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dm_helper.c28 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, in v7m_msr_xpsr() argument
38 if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) { in v7m_msr_xpsr()
41 xpsr_write(env, val, apsrmask); in v7m_msr_xpsr()
45 static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) in v7m_mrs_xpsr() argument
54 if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) { in v7m_mrs_xpsr()
59 return xpsr_read(env) & mask; in v7m_mrs_xpsr()
62 uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure) in arm_v7m_mrs_control() argument
64 uint32_t value = env->v7m.control[secure]; in arm_v7m_mrs_control()
68 value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; in arm_v7m_mrs_control()
75 void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) in HELPER()
[all …]
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
27 DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
28 DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32)
29 DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
[all …]
/openbmc/qemu/target/mips/
H A Dcpu.c66 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) in fpu_dump_state() argument
69 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); in fpu_dump_state()
73 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, in fpu_dump_state()
74 get_float_exception_flags(&env->active_fpu.fp_status)); in fpu_dump_state()
77 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); in fpu_dump_state()
83 CPUMIPSState *env = cpu_env(cs); in mips_cpu_dump_state() local
89 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], in mips_cpu_dump_state()
90 env->hflags, env->btarget, env->bcond); in mips_cpu_dump_state()
96 regnames[i], env->active_tc.gpr[i]); in mips_cpu_dump_state()
104 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); in mips_cpu_dump_state()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dsysemu_helper.h.inc13 DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
14 DEF_HELPER_1(mfc0_mvpconf0, tl, env)
15 DEF_HELPER_1(mfc0_mvpconf1, tl, env)
16 DEF_HELPER_1(mftc0_vpecontrol, tl, env)
17 DEF_HELPER_1(mftc0_vpeconf0, tl, env)
18 DEF_HELPER_1(mfc0_random, tl, env)
19 DEF_HELPER_1(mfc0_tcstatus, tl, env)
20 DEF_HELPER_1(mftc0_tcstatus, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
22 DEF_HELPER_1(mftc0_tcbind, tl, env)
[all …]
H A Dfpu_helper.c40 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) in helper_cfc1() argument
46 arg1 = (int32_t)env->active_fpu.fcr0; in helper_cfc1()
50 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { in helper_cfc1()
51 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_cfc1()
53 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); in helper_cfc1()
55 do_raise_exception(env, EXCP_RI, GETPC()); in helper_cfc1()
61 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in helper_cfc1()
62 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_cfc1()
63 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; in helper_cfc1()
65 helper_raise_exception(env, EXCP_RI); in helper_cfc1()
[all …]
/openbmc/qemu/target/xtensa/
H A Dexc_helper.c37 void HELPER(exception)(CPUXtensaState *env, uint32_t excp) in HELPER()
39 CPUState *cs = env_cpu(env); in HELPER()
43 env->yield_needed = 0; in HELPER()
48 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause) in HELPER()
52 env->pc = pc; in HELPER()
53 if (env->sregs[PS] & PS_EXCM) { in HELPER()
54 if (env->config->ndepc) { in HELPER()
55 env->sregs[DEPC] = pc; in HELPER()
57 env->sregs[EPC1] = pc; in HELPER()
61 env->sregs[EPC1] = pc; in HELPER()
[all …]
H A Dwin_helper.c35 static void copy_window_from_phys(CPUXtensaState *env, in copy_window_from_phys() argument
38 assert(phys < env->config->nareg); in copy_window_from_phys()
39 if (phys + n <= env->config->nareg) { in copy_window_from_phys()
40 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
43 uint32_t n1 = env->config->nareg - phys; in copy_window_from_phys()
44 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
46 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys()
51 static void copy_phys_from_window(CPUXtensaState *env, in copy_phys_from_window() argument
54 assert(phys < env->config->nareg); in copy_phys_from_window()
55 if (phys + n <= env->config->nareg) { in copy_phys_from_window()
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/openbmc/qemu/target/hppa/
H A Dgdbstub.c32 CPUHPPAState *env = cpu_env(cs); in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
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/openbmc/qemu/target/sh4/
H A Dop_helper.c49 void helper_ldtlb(CPUSH4State *env) in helper_ldtlb() argument
52 cpu_abort(env_cpu(env), "Unhandled ldtlb"); in helper_ldtlb()
54 cpu_load_tlb(env); in helper_ldtlb()
59 void raise_exception(CPUSH4State *env, int index, in raise_exception() argument
62 CPUState *cs = env_cpu(env); in raise_exception()
68 void helper_raise_illegal_instruction(CPUSH4State *env) in helper_raise_illegal_instruction() argument
70 raise_exception(env, 0x180, 0); in helper_raise_illegal_instruction()
73 void helper_raise_slot_illegal_instruction(CPUSH4State *env) in helper_raise_slot_illegal_instruction() argument
75 raise_exception(env, 0x1a0, 0); in helper_raise_slot_illegal_instruction()
78 void helper_raise_fpu_disable(CPUSH4State *env) in helper_raise_fpu_disable() argument
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/openbmc/qemu/target/ppc/
H A Dexcp_helper.c112 static void dump_syscall(CPUPPCState *env) in dump_syscall() argument
118 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), in dump_syscall()
119 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), in dump_syscall()
120 ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7), in dump_syscall()
121 ppc_dump_gpr(env, 8), env->nip); in dump_syscall()
124 static void dump_hcall(CPUPPCState *env) in dump_hcall() argument
131 ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4), in dump_hcall()
132 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), in dump_hcall()
133 ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8), in dump_hcall()
134 ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10), in dump_hcall()
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/openbmc/qemu/target/m68k/
H A Dop_helper.c29 static void cf_rte(CPUM68KState *env) in cf_rte() argument
34 sp = env->aregs[7]; in cf_rte()
35 fmt = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); in cf_rte()
36 env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); in cf_rte()
38 env->aregs[7] = sp + 8; in cf_rte()
40 cpu_m68k_set_sr(env, fmt); in cf_rte()
43 static void m68k_rte(CPUM68KState *env) in m68k_rte() argument
49 sp = env->aregs[7]; in m68k_rte()
51 sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); in m68k_rte()
53 env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); in m68k_rte()
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