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Searched refs:env (Results 1 – 25 of 1317) sorted by relevance

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/openbmc/qemu/target/sparc/
H A Dwin_helper.c26 void cpu_set_cwp(CPUSPARCState *env, int new_cwp) in cpu_set_cwp() argument
29 if (env->cwp == env->nwindows - 1) { in cpu_set_cwp()
30 memcpy(env->regbase, env->regbase + env->nwindows * 16, in cpu_set_cwp()
31 sizeof(env->gregs)); in cpu_set_cwp()
33 env->cwp = new_cwp; in cpu_set_cwp()
36 if (new_cwp == env->nwindows - 1) { in cpu_set_cwp()
37 memcpy(env->regbase + env->nwindows * 16, env->regbase, in cpu_set_cwp()
38 sizeof(env->gregs)); in cpu_set_cwp()
40 env->regwptr = env->regbase + (new_cwp * 16); in cpu_set_cwp()
43 target_ulong cpu_get_psr(CPUSPARCState *env) in cpu_get_psr() argument
[all …]
H A Dfop_helper.c47 static void check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra) in check_ieee_exceptions() argument
49 target_ulong status = get_float_exception_flags(&env->fp_status); in check_ieee_exceptions()
54 set_float_exception_flags(0, &env->fp_status); in check_ieee_exceptions()
73 if (cexc & (env->fsr >> FSR_TEM_SHIFT)) { in check_ieee_exceptions()
75 env->fsr_cexc_ftt = cexc | FSR_FTT_IEEE_EXCP; in check_ieee_exceptions()
76 cpu_raise_exception_ra(env, TT_FP_EXCP, ra); in check_ieee_exceptions()
80 env->fsr |= cexc << FSR_AEXC_SHIFT; in check_ieee_exceptions()
84 env->fsr_cexc_ftt = cexc; in check_ieee_exceptions()
87 float32 helper_fadds(CPUSPARCState *env, float32 src1, float32 src2) in helper_fadds() argument
89 float32 ret = float32_add(src1, src2, &env->fp_status); in helper_fadds()
[all …]
/openbmc/qemu/target/i386/
H A Dhelper.h5 DEF_HELPER_3(write_eflags, void, env, tl, i32)
6 DEF_HELPER_1(read_eflags, tl, env)
7 DEF_HELPER_2(divb_AL, void, env, tl)
8 DEF_HELPER_2(idivb_AL, void, env, tl)
9 DEF_HELPER_2(divw_AX, void, env, tl)
10 DEF_HELPER_2(idivw_AX, void, env, tl)
11 DEF_HELPER_2(divl_EAX, void, env, tl)
12 DEF_HELPER_2(idivl_EAX, void, env, tl)
14 DEF_HELPER_2(divq_EAX, void, env, tl)
15 DEF_HELPER_2(idivq_EAX, void, env, tl)
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/openbmc/qemu/target/rx/
H A Dop_helper.c28 void raise_exception(CPURXState *env, int index,
31 static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) in _set_psw() argument
34 prev_u = env->psw_u; in _set_psw()
35 rx_cpu_unpack_psw(env, psw, rte); in _set_psw()
36 if (prev_u != env->psw_u) { in _set_psw()
38 if (env->psw_u) { in _set_psw()
39 env->isp = env->regs[0]; in _set_psw()
40 env->regs[0] = env->usp; in _set_psw()
42 env->usp = env->regs[0]; in _set_psw()
43 env->regs[0] = env->isp; in _set_psw()
[all …]
/openbmc/qemu/target/hppa/
H A Dgdbstub.c32 CPUHPPAState *env = cpu_env(cs); in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
[all …]
/openbmc/qemu/target/xtensa/
H A Dwin_helper.c34 static void copy_window_from_phys(CPUXtensaState *env, in copy_window_from_phys() argument
37 assert(phys < env->config->nareg); in copy_window_from_phys()
38 if (phys + n <= env->config->nareg) { in copy_window_from_phys()
39 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
42 uint32_t n1 = env->config->nareg - phys; in copy_window_from_phys()
43 memcpy(env->regs + window, env->phys_regs + phys, in copy_window_from_phys()
45 memcpy(env->regs + window + n1, env->phys_regs, in copy_window_from_phys()
50 static void copy_phys_from_window(CPUXtensaState *env, in copy_phys_from_window() argument
53 assert(phys < env->config->nareg); in copy_phys_from_window()
54 if (phys + n <= env->config->nareg) { in copy_phys_from_window()
[all …]
H A Dhelper.h1 DEF_HELPER_2(exception, noreturn, env, i32)
2 DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
3 DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
4 DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
6 DEF_HELPER_1(sync_windowbase, void, env)
7 DEF_HELPER_4(entry, void, env, i32, i32, i32)
8 DEF_HELPER_2(test_ill_retw, void, env, i32)
9 DEF_HELPER_2(test_underflow_retw, void, env, i32)
10 DEF_HELPER_2(retw, void, env, i32)
11 DEF_HELPER_3(window_check, noreturn, env, i32, i32)
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dsystem_helper.h.inc13 DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
14 DEF_HELPER_1(mfc0_mvpconf0, tl, env)
15 DEF_HELPER_1(mfc0_mvpconf1, tl, env)
16 DEF_HELPER_1(mftc0_vpecontrol, tl, env)
17 DEF_HELPER_1(mftc0_vpeconf0, tl, env)
18 DEF_HELPER_1(mfc0_random, tl, env)
19 DEF_HELPER_1(mfc0_tcstatus, tl, env)
20 DEF_HELPER_1(mftc0_tcstatus, tl, env)
21 DEF_HELPER_1(mfc0_tcbind, tl, env)
22 DEF_HELPER_1(mftc0_tcbind, tl, env)
[all …]
H A Dfpu_helper.c39 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) in helper_cfc1() argument
45 arg1 = (int32_t)env->active_fpu.fcr0; in helper_cfc1()
49 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { in helper_cfc1()
50 if (env->CP0_Config5 & (1 << CP0C5_UFR)) { in helper_cfc1()
52 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); in helper_cfc1()
54 do_raise_exception(env, EXCP_RI, GETPC()); in helper_cfc1()
60 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { in helper_cfc1()
61 if (env->CP0_Config5 & (1 << CP0C5_UFE)) { in helper_cfc1()
62 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; in helper_cfc1()
64 helper_raise_exception(env, EXCP_RI); in helper_cfc1()
[all …]
/openbmc/qemu/target/riscv/
H A Dfpu_helper.c26 target_ulong riscv_cpu_get_fflags(CPURISCVState *env) in riscv_cpu_get_fflags() argument
28 int soft = get_float_exception_flags(&env->fp_status); in riscv_cpu_get_fflags()
40 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard) in riscv_cpu_set_fflags() argument
50 set_float_exception_flags(soft, &env->fp_status); in riscv_cpu_set_fflags()
53 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode() argument
58 rm = env->frm; in helper_set_rounding_mode()
77 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); in helper_set_rounding_mode()
80 set_float_rounding_mode(softrm, &env->fp_status); in helper_set_rounding_mode()
83 void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) in helper_set_rounding_mode_chkfrm() argument
88 if (unlikely(env->frm >= 5)) { in helper_set_rounding_mode_chkfrm()
[all …]
/openbmc/qemu/target/mips/tcg/system/
H A Dcp0_helper.c38 CPUMIPSState *env = &c->env; in mips_vpe_is_wfi() local
44 return cpu->halted && mips_vpe_active(env); in mips_vpe_is_wfi()
50 CPUMIPSState *env = &c->env; in mips_vp_is_wfi() local
52 return cpu->halted && mips_vp_active(env); in mips_vp_is_wfi()
81 CPUMIPSState *c = &cpu->env; in mips_tc_wake()
91 CPUMIPSState *c = &cpu->env; in mips_tc_sleep()
113 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) in mips_cpu_map_tc() argument
121 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { in mips_cpu_map_tc()
123 *tc = env->current_tc; in mips_cpu_map_tc()
124 return env; in mips_cpu_map_tc()
[all …]
H A Dspecial_helper.c29 target_ulong helper_di(CPUMIPSState *env) in helper_di() argument
31 target_ulong t0 = env->CP0_Status; in helper_di()
33 env->CP0_Status = t0 & ~(1 << CP0St_IE); in helper_di()
37 target_ulong helper_ei(CPUMIPSState *env) in helper_ei() argument
39 target_ulong t0 = env->CP0_Status; in helper_ei()
41 env->CP0_Status = t0 | (1 << CP0St_IE); in helper_ei()
45 static void debug_pre_eret(CPUMIPSState *env) in debug_pre_eret() argument
49 env->active_tc.PC, env->CP0_EPC); in debug_pre_eret()
50 if (env->CP0_Status & (1 << CP0St_ERL)) { in debug_pre_eret()
51 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); in debug_pre_eret()
[all …]
/openbmc/qemu/target/sh4/
H A Dop_helper.c48 void helper_ldtlb(CPUSH4State *env) in helper_ldtlb() argument
51 cpu_abort(env_cpu(env), "Unhandled ldtlb"); in helper_ldtlb()
53 cpu_load_tlb(env); in helper_ldtlb()
58 void raise_exception(CPUSH4State *env, int index, in raise_exception() argument
61 CPUState *cs = env_cpu(env); in raise_exception()
67 void helper_raise_illegal_instruction(CPUSH4State *env) in helper_raise_illegal_instruction() argument
69 raise_exception(env, 0x180, 0); in helper_raise_illegal_instruction()
72 void helper_raise_slot_illegal_instruction(CPUSH4State *env) in helper_raise_slot_illegal_instruction() argument
74 raise_exception(env, 0x1a0, 0); in helper_raise_slot_illegal_instruction()
77 void helper_raise_fpu_disable(CPUSH4State *env) in helper_raise_fpu_disable() argument
[all …]
/openbmc/qemu/target/mips/system/
H A Dcp0_timer.c30 static uint32_t cpu_mips_get_count_val(CPUMIPSState *env) in cpu_mips_get_count_val() argument
34 return env->CP0_Count + in cpu_mips_get_count_val()
35 (uint32_t)clock_ns_to_ticks(env->count_clock, now_ns); in cpu_mips_get_count_val()
38 static void cpu_mips_timer_update(CPUMIPSState *env) in cpu_mips_timer_update() argument
44 wait = env->CP0_Compare - cpu_mips_get_count_val(env); in cpu_mips_timer_update()
49 next_ns = now_ns + clock_ticks_to_ns(env->count_clock, wait); in cpu_mips_timer_update()
50 timer_mod(env->timer, next_ns); in cpu_mips_timer_update()
54 static void cpu_mips_timer_expire(CPUMIPSState *env) in cpu_mips_timer_expire() argument
56 cpu_mips_timer_update(env); in cpu_mips_timer_expire()
57 if (env->insn_flags & ISA_MIPS_R2) { in cpu_mips_timer_expire()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dhelper-mve.h19 DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32)
20 DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32)
21 DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32)
22 DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32)
23 DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32)
24 DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32)
26 DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32)
27 DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32)
28 DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32)
29 DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32)
[all …]
/openbmc/qemu/hw/xtensa/
H A Dpic_cpu.c36 void check_interrupts(CPUXtensaState *env) in check_interrupts() argument
38 CPUState *cs = env_cpu(env); in check_interrupts()
39 int minlevel = xtensa_get_cintlevel(env); in check_interrupts()
40 uint32_t int_set_enabled = env->sregs[INTSET] & in check_interrupts()
41 (env->sregs[INTENABLE] | env->config->inttype_mask[INTTYPE_NMI]); in check_interrupts()
44 if (minlevel >= env->config->nmi_level) { in check_interrupts()
45 minlevel = env->config->nmi_level - 1; in check_interrupts()
47 for (level = env->config->nlevel; level > minlevel; --level) { in check_interrupts()
48 if (env->config->level_mask[level] & int_set_enabled) { in check_interrupts()
49 env->pending_irq_level = level; in check_interrupts()
[all …]
/openbmc/qemu/target/m68k/
H A Dhelper.h4 DEF_HELPER_4(divuw, void, env, int, i32, int)
5 DEF_HELPER_4(divsw, void, env, int, s32, int)
6 DEF_HELPER_5(divul, void, env, int, int, i32, int)
7 DEF_HELPER_5(divsl, void, env, int, int, s32, int)
8 DEF_HELPER_5(divull, void, env, int, int, i32, int)
9 DEF_HELPER_5(divsll, void, env, int, int, s32, int)
10 DEF_HELPER_2(set_sr, void, env, i32)
11 DEF_HELPER_3(cf_movec_to, void, env, i32, i32)
12 DEF_HELPER_3(m68k_movec_to, void, env, i32, i32)
13 DEF_HELPER_2(m68k_movec_from, i32, env, i32)
[all …]
/openbmc/qemu/target/mips/
H A Dinternal.h115 int get_physical_address(CPUMIPSState *env, hwaddr *physical,
144 int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot,
146 void (*helper_tlbwi)(CPUMIPSState *env);
147 void (*helper_tlbwr)(CPUMIPSState *env);
148 void (*helper_tlbp)(CPUMIPSState *env);
149 void (*helper_tlbr)(CPUMIPSState *env);
150 void (*helper_tlbinv)(CPUMIPSState *env);
151 void (*helper_tlbinvf)(CPUMIPSState *env);
159 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
160 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
[all …]
/openbmc/qemu/target/loongarch/tcg/
H A Dfpu_helper.c28 void restore_fp_status(CPULoongArchState *env) in restore_fp_status() argument
30 set_float_rounding_mode(ieee_rm[(env->fcsr0 >> FCSR0_RM) & 0x3], in restore_fp_status()
31 &env->fp_status); in restore_fp_status()
32 set_flush_to_zero(0, &env->fp_status); in restore_fp_status()
33 set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status); in restore_fp_status()
38 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); in restore_fp_status()
39 set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status); in restore_fp_status()
41 set_float_default_nan_pattern(0b01000000, &env->fp_status); in restore_fp_status()
65 static void update_fcsr0_mask(CPULoongArchState *env, uintptr_t pc, int mask) in update_fcsr0_mask() argument
67 int flags = get_float_exception_flags(&env->fp_status); in update_fcsr0_mask()
[all …]
/openbmc/qemu/target/ppc/
H A Dcpu.c31 target_ulong cpu_read_xer(const CPUPPCState *env) in cpu_read_xer() argument
33 if (is_isa300(env)) { in cpu_read_xer()
34 return env->xer | (env->so << XER_SO) | in cpu_read_xer()
35 (env->ov << XER_OV) | (env->ca << XER_CA) | in cpu_read_xer()
36 (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); in cpu_read_xer()
39 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | in cpu_read_xer()
40 (env->ca << XER_CA); in cpu_read_xer()
43 void cpu_write_xer(CPUPPCState *env, target_ulong xer) in cpu_write_xer() argument
45 env->so = (xer >> XER_SO) & 1; in cpu_write_xer()
46 env->ov = (xer >> XER_OV) & 1; in cpu_write_xer()
[all …]
H A Dpower8-pmu.c24 static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) in pmc_has_overflow_enabled() argument
27 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; in pmc_has_overflow_enabled()
30 return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; in pmc_has_overflow_enabled()
37 static void pmu_update_summaries(CPUPPCState *env) in pmu_update_summaries() argument
39 target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0]; in pmu_update_summaries()
40 target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1]; in pmu_update_summaries()
80 env->pmc_ins_cnt = ins_cnt; in pmu_update_summaries()
81 env->pmc_cyc_cnt = cyc_cnt; in pmu_update_summaries()
84 static void hreg_bhrb_filter_update(CPUPPCState *env) in hreg_bhrb_filter_update() argument
88 if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { in hreg_bhrb_filter_update()
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/openbmc/phosphor-power/phosphor-regulators/test/actions/
H A Daction_environment_tests.cpp56 ActionEnvironment env{idMap, "regulator1", services}; in TEST() local
57 EXPECT_EQ(env.getAdditionalErrorData().size(), 0); in TEST()
58 EXPECT_EQ(env.getDevice().getID(), "regulator1"); in TEST()
59 EXPECT_EQ(env.getDeviceID(), "regulator1"); in TEST()
60 EXPECT_EQ(env.getPhaseFaults().size(), 0); in TEST()
61 EXPECT_EQ(env.getRuleDepth(), 0); in TEST()
62 EXPECT_EQ(env.getVolts().has_value(), false); in TEST()
74 ActionEnvironment env{idMap, "", services}; in TEST() local
75 EXPECT_EQ(env.getAdditionalErrorData().size(), 0); in TEST()
77 env.addAdditionalErrorData("foo", "foo_value"); in TEST()
[all …]
/openbmc/qemu/target/hexagon/
H A Dhelper.h21 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
22 DEF_HELPER_2(commit_store, void, env, int)
23 DEF_HELPER_3(gather_store, void, env, i32, int)
24 DEF_HELPER_1(commit_hvx_stores, void, env)
27 DEF_HELPER_3(sfrecipa, i64, env, f32, f32)
28 DEF_HELPER_2(sfinvsqrta, i64, env, f32)
29 DEF_HELPER_5(vacsh_val, s64, env, s64, s64, s64, i32)
30 DEF_HELPER_FLAGS_4(vacsh_pred, TCG_CALL_NO_RWG_SE, s32, env, s64, s64, s64)
35 DEF_HELPER_2(conv_sf2df, f64, env, f32)
36 DEF_HELPER_2(conv_df2sf, f32, env, f64)
[all …]
/openbmc/qemu/target/s390x/
H A Dmachine.c35 kvm_s390_set_cpu_state(cpu, cpu->env.cpu_state); in cpu_post_load()
70 VMSTATE_UINT64(env.vregs[0][0], S390CPU),
71 VMSTATE_UINT64(env.vregs[1][0], S390CPU),
72 VMSTATE_UINT64(env.vregs[2][0], S390CPU),
73 VMSTATE_UINT64(env.vregs[3][0], S390CPU),
74 VMSTATE_UINT64(env.vregs[4][0], S390CPU),
75 VMSTATE_UINT64(env.vregs[5][0], S390CPU),
76 VMSTATE_UINT64(env.vregs[6][0], S390CPU),
77 VMSTATE_UINT64(env.vregs[7][0], S390CPU),
78 VMSTATE_UINT64(env.vregs[8][0], S390CPU),
[all …]
/openbmc/qemu/target/s390x/tcg/
H A Dfpu_helper.c60 static void handle_exceptions(CPUS390XState *env, bool XxC, uintptr_t retaddr) in handle_exceptions() argument
66 qemu_exc = env->fpu_status.float_exception_flags; in handle_exceptions()
70 env->fpu_status.float_exception_flags = 0; in handle_exceptions()
82 !((env->fpc >> 24) & S390_IEEE_MASK_UNDERFLOW)) { in handle_exceptions()
102 if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) { in handle_exceptions()
104 tcg_s390_data_exception(env, s390_exc, retaddr); in handle_exceptions()
107 env->fpc |= (s390_exc & ~S390_IEEE_MASK_INEXACT) << 16; in handle_exceptions()
113 if (s390_exc & S390_IEEE_MASK_INEXACT & env->fpc >> 24) { in handle_exceptions()
114 tcg_s390_data_exception(env, s390_exc & S390_IEEE_MASK_INEXACT, in handle_exceptions()
118 env->fpc |= (s390_exc & S390_IEEE_MASK_INEXACT) << 16; in handle_exceptions()
[all …]

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