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Searched refs:eaddr (Results 1 – 13 of 13) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dmmu-radix64.c65 vaddr eaddr, in ppc_radix64_get_fully_qualified_addr() argument
69 if (eaddr & ~R_EADDR_VALID_MASK) { in ppc_radix64_get_fully_qualified_addr()
74 switch (eaddr & R_EADDR_QUADRANT) { in ppc_radix64_get_fully_qualified_addr()
95 switch (eaddr & R_EADDR_QUADRANT) { in ppc_radix64_get_fully_qualified_addr()
116 vaddr eaddr) in ppc_radix64_raise_segi() argument
130 env->spr[SPR_DAR] = eaddr; in ppc_radix64_raise_segi()
145 vaddr eaddr, uint32_t cause) in ppc_radix64_raise_si() argument
152 eaddr, cause); in ppc_radix64_raise_si()
167 env->spr[SPR_DAR] = eaddr; in ppc_radix64_raise_si()
176 vaddr eaddr, hwaddr g_raddr, uint32_t cause) in ppc_radix64_raise_hsi() argument
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H A Dmmu_common.c69 int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr, in ppc6xx_tlb_getnum() argument
75 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1); in ppc6xx_tlb_getnum()
89 target_ulong eaddr, MMUAccessType access_type, in ppc6xx_tlb_check() argument
102 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); in ppc6xx_tlb_check()
105 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) { in ppc6xx_tlb_check()
110 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr); in ppc6xx_tlb_check()
117 tlb->EPN, eaddr, tlb->pte1, in ppc6xx_tlb_check()
191 target_ulong eaddr, MMUAccessType access_type, in get_bat_6xx_tlb() argument
200 ifetch ? 'I' : 'D', eaddr); in get_bat_6xx_tlb()
215 ifetch ? 'I' : 'D', i, eaddr, *BATu, *BATl); in get_bat_6xx_tlb()
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H A Dmmu-hash32.c114 target_ulong eaddr, in ppc_hash32_direct_store() argument
145 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
150 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
164 *raddr = eaddr; in ppc_hash32_direct_store()
170 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
187 *raddr = eaddr; in ppc_hash32_direct_store()
194 env->spr[SPR_DAR] = eaddr; in ppc_hash32_direct_store()
255 target_ulong sr, target_ulong eaddr, in ppc_hash32_htab_lookup() argument
263 pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS; in ppc_hash32_htab_lookup()
294 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, in ppc_hash32_xlate() argument
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H A Dmmu-hash64.c53 static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) in slb_lookup() argument
59 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); in slb_lookup()
61 esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; in slb_lookup()
62 esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; in slb_lookup()
708 ppc_slb_t *slb, target_ulong eaddr, in ppc_hash64_htab_lookup() argument
734 epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; in ppc_hash64_htab_lookup()
739 epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; in ppc_hash64_htab_lookup()
982 bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, in ppc_hash64_xlate() argument
1012 raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; in ppc_hash64_xlate()
1021 if (!(eaddr >> 63)) { in ppc_hash64_xlate()
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H A Dmmu-booke.c476 bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, in ppc_booke_xlate() argument
486 ret = mmubooke206_get_physical_address(env, &raddr, &prot, eaddr, in ppc_booke_xlate()
489 ret = mmubooke_get_physical_address(env, &raddr, &prot, eaddr, in ppc_booke_xlate()
507 booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx); in ppc_booke_xlate()
511 env->spr[SPR_BOOKE_DEAR] = eaddr; in ppc_booke_xlate()
519 env->spr[SPR_BOOKE_DEAR] = eaddr; in ppc_booke_xlate()
H A Dmmu-radix64.h17 bool ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
H A Dmmu-booke.h13 bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
H A Dmmu_helper.c60 target_ulong eaddr, in ppc6xx_tlb_invalidate_virt2() argument
70 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code); in ppc6xx_tlb_invalidate_virt2()
72 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) { in ppc6xx_tlb_invalidate_virt2()
74 TARGET_FMT_lx "\n", nr, env->nb_tlb, eaddr); in ppc6xx_tlb_invalidate_virt2()
86 target_ulong eaddr, int is_code) in ppc6xx_tlb_invalidate_virt() argument
88 ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0); in ppc6xx_tlb_invalidate_virt()
1361 bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, in ppc_cpu_tlb_fill() argument
1369 if (ppc_xlate(cpu, eaddr, access_type, &raddr, in ppc_cpu_tlb_fill()
1371 tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, in ppc_cpu_tlb_fill()
H A Dinternal.h248 bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
253 int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
H A Dmmu-hash32.h8 bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
H A Dmmu-hash64.h10 bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Datmel_nand_ecc.h48 u32 eaddr; /* 0x0C PMECC End Address Register */ member
H A Datmel_nand.c673 pmecc_writel(host->pmecc, eaddr, in atmel_pmecc_core_init()