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Searched refs:dx_base (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/dram/
H A Dcmd_ddrphy.c88 void __iomem *phy_base, *dx_base; in dump_loop() local
93 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
97 (*callback)(dx_base); in dump_loop()
98 dx_base += PHY_DX_STRIDE; in dump_loop()
108 print_bdl(dx_base + PHY_DX_BDLR0, 5); in __wbdl_dump()
109 print_bdl(dx_base + PHY_DX_BDLR1, 5); in __wbdl_dump()
125 print_bdl(dx_base + PHY_DX_BDLR3, 5); in __rbdl_dump()
126 print_bdl(dx_base + PHY_DX_BDLR4, 4); in __rbdl_dump()
144 u32 gtr = readl(dx_base + PHY_DX_GTR); in __wld_dump()
167 u32 gtr = readl(dx_base + PHY_DX_GTR); in __dqsgd_dump()
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H A Dcmd_ddrmphy.c73 void __iomem *phy_base, *dx_base; in dump_loop() local
78 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
82 (*callback)(dx_base); in dump_loop()
83 dx_base += MPHY_DX_STRIDE; in dump_loop()
129 print_bdl(dx_base + MPHY_DX_BDLR0, 4); in __wbdl_dump()
130 print_bdl(dx_base + MPHY_DX_BDLR1, 4); in __wbdl_dump()
131 print_bdl(dx_base + MPHY_DX_BDLR2, 2); in __wbdl_dump()
147 print_bdl(dx_base + MPHY_DX_BDLR3, 4); in __rbdl_dump()
148 print_bdl(dx_base + MPHY_DX_BDLR4, 4); in __rbdl_dump()
149 print_bdl(dx_base + MPHY_DX_BDLR5, 1); in __rbdl_dump()
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H A Dumc-pxs2.c103 lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1); in ddrphy_dqs_delay_fixup()
107 writel(lcdlr1, dx_base + MPHY_DX_LCDLR1); in ddrphy_dqs_delay_fixup()
108 readl(dx_base + MPHY_DX_LCDLR1); /* relax */ in ddrphy_dqs_delay_fixup()
109 dx_base += MPHY_DX_STRIDE; in ddrphy_dqs_delay_fixup()
124 gtr = readl(dx_base + MPHY_DX_GTR); in ddrphy_get_system_latency()
134 dx_base += MPHY_DX_STRIDE; in ddrphy_get_system_latency()
147 void __iomem *zq_base, *dx_base; in ddrphy_init() local
218 dx_base = phy_base + MPHY_DX_BASE; in ddrphy_init()
220 tmp = readl(dx_base + MPHY_DX_GCR0); in ddrphy_init()
224 writel(tmp, dx_base + MPHY_DX_GCR0); in ddrphy_init()
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H A Dddrphy-training.c23 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training() local
28 tmp = readl(dx_base + PHY_DX_GCR); in ddrphy_prepare_training()
33 writel(tmp, dx_base + PHY_DX_GCR); in ddrphy_prepare_training()
34 dx_base += PHY_DX_STRIDE; in ddrphy_prepare_training()