Searched refs:dwc_ddrphy_apb_wr (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/drivers/ddr/imx/imx8m/ |
| H A D | ddrphy_train.c | 24 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); in ddr_cfg_phy()
36 dwc_ddrphy_apb_wr(0xd0000, 0x0); in ddr_cfg_phy()
43 dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val); in ddr_cfg_phy()
57 dwc_ddrphy_apb_wr(0xd0000, 0x1); in ddr_cfg_phy()
58 dwc_ddrphy_apb_wr(0xd0099, 0x9); in ddr_cfg_phy()
59 dwc_ddrphy_apb_wr(0xd0099, 0x1); in ddr_cfg_phy()
60 dwc_ddrphy_apb_wr(0xd0099, 0x0); in ddr_cfg_phy()
66 dwc_ddrphy_apb_wr(0xd0099, 0x1); in ddr_cfg_phy()
69 dwc_ddrphy_apb_wr(0xd0000, 0x0); in ddr_cfg_phy()
71 dwc_ddrphy_apb_wr(0xd0000, 0x1); in ddr_cfg_phy()
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| H A D | helper.c | 109 dwc_ddrphy_apb_wr(0xd0000, 0x0); in ddrphy_trained_csr_save()
110 dwc_ddrphy_apb_wr(0xc0080, 0x3); in ddrphy_trained_csr_save()
116 dwc_ddrphy_apb_wr(0xc0080, 0x2); in ddrphy_trained_csr_save()
117 dwc_ddrphy_apb_wr(0xd0000, 0x1); in ddrphy_trained_csr_save()
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| /openbmc/u-boot/arch/arm/include/asm/arch-imx8m/ |
| H A D | ddr.h | 732 #define dwc_ddrphy_apb_wr(addr, data) \ macro
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