Searched refs:dv_pll1_regs (Results 1 – 2 of 2) sorted by relevance
114 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); in dm365_pll2_init()115 setbits_le32(&dv_pll1_regs->pllctl, in dm365_pll2_init()125 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()138 writel(pllm, &dv_pll1_regs->pllm); in dm365_pll2_init()139 writel(prediv, &dv_pll1_regs->prediv); in dm365_pll2_init()141 writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); in dm365_pll2_init()145 PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); in dm365_pll2_init()148 &dv_pll1_regs->secctl); in dm365_pll2_init()150 writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl); in dm365_pll2_init()162 writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd); in dm365_pll2_init()[all …]
75 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE) macro