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Searched refs:dv_ddr2_regs_ctrl (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-davinci/
H A Dda850_lowlevel.c187 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); in da850_ddr_setup()
206 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK); in da850_ddr_setup()
216 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()
222 &dv_ddr2_regs_ctrl->sdbcr2); in da850_ddr_setup()
224 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); in da850_ddr_setup()
225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); in da850_ddr_setup()
229 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr); in da850_ddr_setup()
238 &dv_ddr2_regs_ctrl->sdrcr); in da850_ddr_setup()
246 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, in da850_ddr_setup()
248 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); in da850_ddr_setup()
H A Ddm365_lowlevel.c216 writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); in dm365_ddr_setup()
220 &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
222 &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
225 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); in dm365_ddr_setup()
227 writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); in dm365_ddr_setup()
229 writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); in dm365_ddr_setup()
231 writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr); in dm365_ddr_setup()
234 writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr); in dm365_ddr_setup()
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dddr2_defs.h13 struct dv_ddr2_regs_ctrl { struct
80 #define dv_ddr2_regs_ctrl \ macro
81 ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)