Searched refs:dtpr1 (Results 1 – 16 of 16) sorted by relevance
| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 28 .dtpr1 = 0x328341E0ul,
68 .dtpr1 = 0x32845A80ul,
129 .dtpr1 = 0x32834200ul,
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| H A D | ddr3_cfg.c | 26 .dtpr1 = 0x12868300ul,
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 26 unsigned int dtpr1; member
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| /openbmc/u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 298 .dtpr1 = 0x00400860,
342 .dtpr1 = 0x005608a0,
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 83 u32 dtpr1; member
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 135 u32 dtpr1; member
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| H A D | stm32mp1_ddr_regs.h | 155 u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/ member
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| H A D | stm32mp1_ddr.c | 144 DDRPHY_REG_TIMING(dtpr1),
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 32 debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1); in dump_phy_config()
330 spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | in init_ddr3param()
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| H A D | ddr3.c | 50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); in ddr3_init_ddrphy()
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 84 writel(ddr_config->dtpr1, ddr_phy_regs + DDRP_DTPR1); in ddr_phy_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 182 u32 dtpr1; /* 0x4c dram timing parameters register 1 */ member
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| H A D | dram_sun6i.h | 171 u32 dtpr1; /* 0x38 dram timing parameters register 1 */ member
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| /openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/ |
| H A D | jz4780_dram.h | 445 u32 dtpr1; /* DRAM Timing Parameters Register 1 */ member
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 90 dtpr1
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun6i.c | 141 (MCTL_TAOND << 0), &mctl_phy->dtpr1); in mctl_channel_init()
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