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Searched refs:drate (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing.c1281 .drate = 3200,
1288 .drate = 400,
1295 .drate = 100,
1302 .drate = 3200,
H A Dlpddr4_timing_b0.c1155 .drate = 3200,
1162 .drate = 667,
1169 .drate = 3200,
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddrphy_train.c31 debug("DRAM PHY training for %dMTS\n", fsp_msg->drate); in ddr_cfg_phy()
33 ddrphy_init_set_dfi_clk(fsp_msg->drate); in ddr_cfg_phy()
H A Dddrphy_utils.c106 void ddrphy_init_set_dfi_clk(unsigned int drate) in ddrphy_init_set_dfi_clk() argument
108 switch (drate) { in ddrphy_init_set_dfi_clk()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h677 unsigned int drate; member
714 void ddrphy_init_set_dfi_clk(unsigned int drate);