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Searched refs:dram_timing4 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dsdram_gen5.h29 u32 dram_timing4; /* 0x10 */ member
88 u32 dram_timing4; member
/openbmc/u-boot/drivers/ddr/altera/
H A Dsdram_gen5.c343 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4); in sdr_load_regs()
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dwrap_sdram_config.c68 .dram_timing4 =