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Searched refs:dram_clock_change_latency_us (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c205 .dram_clock_change_latency_us = 23.84,
299 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
307 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
319 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached; in calculate_wm_set_for_vlevel()
380 if ((int)(dcn3_01_soc.dram_clock_change_latency_us * 1000) in dcn301_update_bw_bounding_box()
383 dcn3_01_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000.0; in dcn301_update_bw_bounding_box()
403 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn301_fpu_init_soc_bounding_box()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
651 if ((int)(dcn3_1_soc.dram_clock_change_latency_us * 1000) in dcn31_update_bw_bounding_box()
654 dcn3_1_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn31_update_bw_bounding_box()
712 if ((int)(dcn3_15_soc.dram_clock_change_latency_us * 1000) in dcn315_update_bw_bounding_box()
715 dcn3_15_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn315_update_bw_bounding_box()
804 if ((int)(dcn3_16_soc.dram_clock_change_latency_us * 1000) in dcn316_update_bw_bounding_box()
807 dcn3_16_soc.dram_clock_change_latency_us = dc->debug.dram_clock_change_latency_ns / 1000; in dcn316_update_bw_bounding_box()
825 return (int)(soc->dram_clock_change_latency_us * pix_clk_100hz * bpp in dcn_get_approx_det_segs_required_for_pstate()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c167 .dram_clock_change_latency_us = 404,
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
413 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
437 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
483 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
504 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
586 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_fpu_calculate_wm_and_dlg()
703 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn30_find_dummy_latency_index_for_fw_based_mclk_switch()
731 double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_fpu_build_wm_range_table()
[all …]
H A Ddisplay_rq_dlg_calc_30.c1244 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h71 uint32_t dram_clock_change_latency_us; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn10/
H A Ddcn10_fpu.c122 .dram_clock_change_latency_us = 17.0,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c155 .dram_clock_change_latency_us = 404,
355 dcn3_02_soc.dram_clock_change_latency_us = in dcn302_fpu_init_soc_bounding_box()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c154 .dram_clock_change_latency_us = 404,
362 dcn3_03_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10; in dcn303_fpu_init_soc_bounding_box()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c155 .dram_clock_change_latency_us = 400,
635 if ((int)(dcn3_21_soc.dram_clock_change_latency_us * 1000) in dcn321_update_bw_bounding_box_fpu()
638 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
662 dcn3_21_soc.dram_clock_change_latency_us = in dcn321_update_bw_bounding_box_fpu()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c320 .dram_clock_change_latency_us = 404.0,
431 .dram_clock_change_latency_us = 404.0,
542 .dram_clock_change_latency_us = 45.0,
756 .dram_clock_change_latency_us = 23.84,
2005 if ((int)(bb->dram_clock_change_latency_us * 1000) in dcn20_patch_bounding_box()
2008 bb->dram_clock_change_latency_us = in dcn20_patch_bounding_box()
2083 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us; in dcn20_validate_bandwidth_fp()
2121 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us; in dcn20_validate_bandwidth_fp()
2207 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us; in calculate_wm_set_for_vlevel()
2215 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
[all …]
H A Ddisplay_rq_dlg_calc_20.c1093 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20_rq_dlg_get_dlg_params()
H A Ddisplay_rq_dlg_calc_20v2.c1094 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us in dml20v2_rq_dlg_get_dlg_params()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c166 .dram_clock_change_latency_us = 400,
176 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn32_build_wm_range_table_fpu()
278 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
2002 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2035 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2158 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2179 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2271 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_calculate_wm_and_dlg_fpu()
2723 if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000) in dcn32_update_bw_bounding_box_fpu()
2726 dcn3_2_soc.dram_clock_change_latency_us = in dcn32_update_bw_bounding_box_fpu()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h235 double dram_clock_change_latency_us; member
H A Ddml1_display_rq_dlg_calc.c1308 mode_lib->soc.dram_clock_change_latency_us in dml1_rq_dlg_get_dlg_params()
1324 (double) mode_lib->soc.dram_clock_change_latency_us); in dml1_rq_dlg_get_dlg_params()
H A Ddisplay_mode_vba.c358 mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us; in fetch_socbb_params()
359 mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us; in fetch_socbb_params()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c228 .dram_clock_change_latency_us = 250.0,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_rq_dlg_calc_21.c1141 mode_lib->soc.dram_clock_change_latency_us in dml_rq_dlg_get_dlg_params()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1714 dc->dml.soc.dram_clock_change_latency_us = dc->dcn_soc->dram_clock_change_latency; in dcn_bw_sync_calcs_and_dml()