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Searched refs:dram_cfg_param (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c13 static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
136 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
321 static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
399 static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
475 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
554 static struct dram_cfg_param lpddr4_phy_pie[] = {
H A Dlpddr4_timing.c13 struct dram_cfg_param lpddr4_ddrc_cfg[] = {
134 struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
328 struct dram_cfg_param lpddr4_fsp0_cfg[] = {
434 struct dram_cfg_param lpddr4_fsp1_cfg[] = {
516 struct dram_cfg_param lpddr4_fsp2_cfg[] = {
593 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
687 struct dram_cfg_param lpddr4_phy_pie[] = {
/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dhelper.c103 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, in ddrphy_trained_csr_save()
125 struct dram_cfg_param *cfg; in dram_config_save()
136 cfg = (struct dram_cfg_param *)(saved_timing_base + in dram_config_save()
H A Dddrphy_csr.c10 struct dram_cfg_param ddrphy_trained_csr[] = {
H A Dddr4_init.c14 void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in ddr4_cfg_umctl2()
H A Dddrphy_train.c13 struct dram_cfg_param *dram_cfg; in ddr_cfg_phy()
H A Dlpddr4_init.c16 void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in lpddr4_cfg_umctl2()
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h671 struct dram_cfg_param { struct
679 struct dram_cfg_param *fsp_cfg; argument
685 struct dram_cfg_param *ddrc_cfg;
688 struct dram_cfg_param *ddrphy_cfg;
694 struct dram_cfg_param *ddrphy_trained_csr;
697 struct dram_cfg_param *ddrphy_pie;
709 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
737 extern struct dram_cfg_param ddrphy_trained_csr[];