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Searched refs:dprefclk_khz (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c193 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT); in dcn201_clk_mgr_construct()
194 clk_mgr->base.dprefclk_khz *= 100; in dcn201_clk_mgr_construct()
196 if (clk_mgr->base.dprefclk_khz == 0) in dcn201_clk_mgr_construct()
197 clk_mgr->base.dprefclk_khz = 600000; in dcn201_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct()
143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c160 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
165 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn301_smu_set_dprefclk()
H A Dvg_clk_mgr.c725 clk_mgr->base.base.dprefclk_khz = 600000; in vg_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h242 uint32_t dprefclk_khz; member
310 …int dprefclk_khz; // Used by program pixel clock in clock source funcs, need to figureout where th… member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.c178 return clk_mgr->base.dprefclk_khz; in dcn31_smu_set_dprefclk()
183 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn31_smu_set_dprefclk()
H A Ddcn31_clk_mgr.c735 clk_mgr->base.base.dprefclk_khz = 600000; in dcn31_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_smu.c196 return clk_mgr->base.dprefclk_khz; in dcn314_smu_set_dprefclk()
201 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in dcn314_smu_set_dprefclk()
H A Ddcn314_clk_mgr.c779 clk_mgr->base.base.dprefclk_khz = 600000; in dcn314_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_vbios_smu.c154 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
H A Drv1_clk_mgr.c334 clk_mgr->base.dprefclk_khz = 600000; in rv1_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c663 clk_mgr->base.base.dprefclk_khz = 600000; in dcn315_clk_mgr_construct()
664 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); in dcn315_clk_mgr_construct()
665 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn315_clk_mgr_construct()
667 …ks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz); in dcn315_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr_vbios_smu.c169 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rn_vbios_smu_set_dprefclk()
H A Drn_clk_mgr.c765 clk_mgr->base.dprefclk_khz = 600000; in rn_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c642 clk_mgr->base.base.dprefclk_khz = 600000; in dcn316_clk_mgr_construct()
643 clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base); in dcn316_clk_mgr_construct()
644 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz; in dcn316_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c178 return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
934 clk_mgr_dce->dprefclk_khz = 600000; in dce120_clk_mgr_create()
955 clk_mgr_dce->dprefclk_khz = 625000; in dce121_clk_mgr_create()
H A Ddce_clock_source.c969 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; in dcn31_program_pix_clk()
1099 clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, in get_pixel_clk_frequency_100hz()
1185 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); in dcn20_program_pix_clk()
1221 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; in dcn3_program_pix_clk()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c540 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn3_clk_mgr_construct()
554 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000; in dcn3_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c553 clk_mgr->base.dprefclk_khz = 700000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved in dcn20_clk_mgr_construct()
581 clk_mgr->base.dprefclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn20_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c991 clk_mgr->base.dprefclk_khz = 716666; in dcn32_clk_mgr_construct()
1016 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk; in dcn32_clk_mgr_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c2122 dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; in dcn10_align_pixel_clocks()