Searched refs:dpa_offset (Results 1 – 4 of 4) sorted by relevance
39 u64 dpa_offset, hpa_offset, bits_upper, mask_upper, hpa; in cxl_dpa_to_hpa() local59 dpa_offset = dpa - cxl_dpa_resource_start(cxled); in cxl_dpa_to_hpa()64 hpa_offset = (dpa_offset & mask_upper) << eiw; in cxl_dpa_to_hpa()67 bits_upper = (dpa_offset & mask_upper) >> (eig + 8); in cxl_dpa_to_hpa()73 hpa_offset |= dpa_offset & GENMASK_ULL(eig + 7, 0); in cxl_dpa_to_hpa()
1129 if (!cxl_type3_dpa(ct3d, host_addr, dpa_offset)) { in cxl_type3_hpa_to_as_and_dpa()1137 if (*dpa_offset < vmr_size) { in cxl_type3_hpa_to_as_and_dpa()1139 } else if (*dpa_offset < vmr_size + pmr_size) { in cxl_type3_hpa_to_as_and_dpa()1141 *dpa_offset -= vmr_size; in cxl_type3_hpa_to_as_and_dpa()1148 *dpa_offset -= (vmr_size + pmr_size); in cxl_type3_hpa_to_as_and_dpa()1158 uint64_t dpa_offset = 0; in cxl_type3_read() local1180 uint64_t dpa_offset = 0; in cxl_type3_write() local1323 if (dpa_offset < vmr_size) { in set_cacheline()1325 } else if (dpa_offset < vmr_size + pmr_size) { in set_cacheline()1327 dpa_offset -= vmr_size; in set_cacheline()[all …]
609 bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset,
447 u64 dpa_offset; member