Searched refs:divr2 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 73 int divr2, divf2; member
136 do_div(temp_setup->vco2, temp_setup->divr2 + 1); in clk_sscg_divq_lookup()
175 for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX; in clk_sscg_divr2_lookup()
176 temp_setup->divr2++) { in clk_sscg_divr2_lookup()
178 do_div(temp_setup->ref_div2, temp_setup->divr2 + 1); in clk_sscg_divr2_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
336 divr2 = FIELD_GET(PLL_DIVR2_MASK, val); in clk_sscg_pll_recalc_rate()
348 do_div(temp64, (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
377 val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2); in clk_sscg_pll_set_rate()
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| /openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock.c | 82 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> in decode_sscg_pll()
242 (divr2 + 1) * (divf2 + 1) / (divq + 1); in decode_sscg_pll()
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