Searched refs:divr1 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 72 int divr1, divf1; member
214 do_div(vco1, temp_setup->divr1 + 1); in clk_sscg_divf1_lookup()
233 for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX; in clk_sscg_divr1_lookup()
234 temp_setup->divr1++) { in clk_sscg_divr1_lookup()
236 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1); in clk_sscg_divr1_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
335 divr1 = FIELD_GET(PLL_DIVR1_MASK, val); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
376 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); in clk_sscg_pll_set_rate()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32h7.c | 501 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
538 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
539 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
548 __func__, divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
561 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
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| /openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock.c | 82 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> in decode_sscg_pll()
241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / in decode_sscg_pll()
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