Searched refs:divq (Results 1 – 6 of 6) sorted by relevance
| /openbmc/u-boot/drivers/clk/sifive/ |
| H A D | wrpll-cln28hpc.c | 160 u8 divq = 0; in __wrpll_calc_divq() local
169 divq = 1; in __wrpll_calc_divq()
172 divq = ilog2(MAX_DIVQ_DIVISOR); in __wrpll_calc_divq()
175 divq = ilog2(s); in __wrpll_calc_divq()
176 *vco_rate = target_rate << divq; in __wrpll_calc_divq()
180 return divq; in __wrpll_calc_divq()
247 u8 fbdiv, divq, best_r, r; in analogbits_wrpll_configure_for_rate() local
288 divq = __wrpll_calc_divq(target_rate, &target_vco_rate); in analogbits_wrpll_configure_for_rate()
289 if (divq == 0) in analogbits_wrpll_configure_for_rate()
291 c->divq = divq; in analogbits_wrpll_configure_for_rate()
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| H A D | analogbits-wrpll-cln28hpc.h | 78 u8 divq; member
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| H A D | fu540-prci.c | 274 c->divq = v; in __prci_wrpll_unpack()
310 r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; in __prci_wrpll_pack()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32h7.c | 323 u8 divq; member
336 .divq = 2,
398 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; in configure_clocks()
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| /openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock.c | 82 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
232 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> in decode_sscg_pll()
242 (divr2 + 1) * (divf2 + 1) / (divq + 1); in decode_sscg_pll()
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| /openbmc/qemu/tests/tcg/i386/ |
| H A D | x86.csv | 566 "DIV r/m64","DIVQ r/m64","divq r/m64","REX.W F7 /6","N.S.","V","","","r","Y","64"
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