Searched refs:divf1 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-sscg-pll.c | 72 int divr1, divf1; member
210 for (temp_setup->divf1 = 0; temp_setup->divf1 <= PLL_DIVF1_MAX; in clk_sscg_divf1_lookup()
211 temp_setup->divf1++) { in clk_sscg_divf1_lookup()
216 vco1 *= temp_setup->divf1 + 1; in clk_sscg_divf1_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
337 divf1 = FIELD_GET(PLL_DIVF1_MASK, val); in clk_sscg_pll_recalc_rate()
351 temp64 *= (divf1 + 1) * (divf2 + 1); in clk_sscg_pll_recalc_rate()
374 val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1); in clk_sscg_pll_set_rate()
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| /openbmc/u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock.c | 82 u32 divr1, divr2, divf1, divf2, divq, div; in decode_sscg_pll() local
228 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> in decode_sscg_pll()
241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / in decode_sscg_pll()
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