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Searched refs:div_reg (Results 1 – 25 of 27) sorted by relevance

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/openbmc/linux/drivers/clk/socfpga/
H A Dclk-periph.c26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate-a10.c29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
46 u32 div_reg[3]; in __socfpga_gate_init() local
77 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
79 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
80 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
81 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
83 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
H A Dclk-periph-a10.c28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
H A Dclk-gate.c96 else if (socfpgaclk->div_reg) { in socfpga_clk_get_div()
97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_get_div()
100 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_get_div()
140 u32 div_reg[3]; in socfpga_gate_init() local
176 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
178 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
179 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
180 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
182 socfpga_clk->div_reg = NULL; in socfpga_gate_init()
H A Dclk-gate-s10.c29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
150 socfpga_clk->div_reg = NULL; in s10_register_gate()
205 if (clks->div_reg) in agilex_register_gate()
206 socfpga_clk->div_reg = regbase + clks->div_reg; in agilex_register_gate()
208 socfpga_clk->div_reg = NULL; in agilex_register_gate()
H A Dclk.h47 void __iomem *div_reg; member
59 void __iomem *div_reg; member
H A Dstratix10-clk.h68 unsigned long div_reg; member
/openbmc/linux/drivers/clk/bcm/
H A Dclk-bcm2835.c492 u32 div_reg; member
1945 .div_reg = CM_OTPDIV,
1975 .div_reg = CM_TECDIV,
1992 .div_reg = CM_ISPDIV,
2005 .div_reg = CM_SDCDIV,
2013 .div_reg = CM_V3DDIV,
2027 .div_reg = CM_VPUDIV,
2063 .div_reg = CM_DFTDIV,
2070 .div_reg = CM_DPIDIV,
2100 .div_reg = CM_GP0DIV,
[all …]
/openbmc/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c410 int div_reg; member
425 .div_reg = CLK_AUDDIV_2,
438 .div_reg = CLK_AUDDIV_2,
451 .div_reg = CLK_AUDDIV_2,
464 .div_reg = CLK_AUDDIV_2,
477 .div_reg = CLK_AUDDIV_3,
490 .div_reg = CLK_AUDDIV_2,
500 .div_reg = CLK_AUDDIV_3,
513 .div_reg = CLK_AUDDIV_3,
526 .div_reg = CLK_AUDDIV_4,
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-sn-f-ospi.c192 u32 div_reg; in f_ospi_config_clk() local
198 div_reg = OSPI_CLK_CTL_DIV_1; in f_ospi_config_clk()
201 div_reg = OSPI_CLK_CTL_DIV_1; in f_ospi_config_clk()
203 div_reg = OSPI_CLK_CTL_DIV_2; in f_ospi_config_clk()
205 div_reg = OSPI_CLK_CTL_DIV_4; in f_ospi_config_clk()
207 div_reg = OSPI_CLK_CTL_DIV_8; in f_ospi_config_clk()
211 div_reg = OSPI_CLK_CTL_DIV_8; in f_ospi_config_clk()
224 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg); in f_ospi_config_clk()
/openbmc/linux/drivers/clk/
H A Dclk-vt8500.c22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
189 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
225 u32 en_reg, div_reg; in vtwm_device_clk_init() local
255 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
257 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
H A Dclk-en7523.c38 u16 div_reg; member
110 .div_reg = REG_SPI_CLK_DIV_SEL,
184 reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7523_get_div()
H A Dclk-k210.c34 u8 div_reg; member
54 .div_reg = (_reg), \
756 if (!cfg->div_reg) in k210_clk_get_rate()
759 reg = readl(ksc->regs + cfg->div_reg); in k210_clk_get_rate()
H A Dclk-bm1880.c116 u32 div_reg; member
151 .div_reg = _div_reg, \
811 div_hws->div.reg = clks->div_reg; in bm1880_clk_register_composite()
/openbmc/u-boot/drivers/clk/altera/
H A Dclk-arria10.c32 u16 div_reg; member
155 if (plat->div_reg) { in socfpga_a10_clk_get_rate()
156 reg = readl(plat->regs + plat->div_reg); in socfpga_a10_clk_get_rate()
333 plat->div_reg = divreg[0]; in socfpga_a10_ofdata_to_platdata()
/openbmc/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c225 u32 div_reg; member
241 void __iomem *div_reg; member
371 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
373 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
431 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mtk.h189 u32 div_reg; member
200 .div_reg = _reg, \
H A Dclk-mt8167-apmixedsys.c81 .div_reg = _reg, \
H A Dclk-mt8516.c473 .div_reg = _reg, \
H A Dclk-mt8167.c662 .div_reg = _reg, \
H A Dclk-mt8365.c546 .div_reg = _reg, \
/openbmc/linux/drivers/clk/samsung/
H A Dclk-cpu.c69 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
74 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
78 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
/openbmc/linux/drivers/gpio/
H A Dgpio-rockchip.c202 unsigned long flags, div_reg, freq, max_debounce; in rockchip_gpio_set_debounce() local
215 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; in rockchip_gpio_set_debounce()
228 if (cur_div_reg < div_reg) in rockchip_gpio_set_debounce()
229 writel(div_reg, bank->reg_base + in rockchip_gpio_set_debounce()
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c461 u32 div_reg = readl(&scu->uart_24m_ref_uxclk); in ast2600_get_uart_uxclk_rate() local
464 u32 n = (div_reg >> 8) & 0x3ff; in ast2600_get_uart_uxclk_rate()
465 u32 r = div_reg & 0xff; in ast2600_get_uart_uxclk_rate()
475 u32 div_reg = readl(&scu->uart_24m_ref_huxclk); in ast2600_get_uart_huxclk_rate() local
479 u32 n = (div_reg >> 8) & 0x3ff; in ast2600_get_uart_huxclk_rate()
480 u32 r = div_reg & 0xff; in ast2600_get_uart_huxclk_rate()
/openbmc/linux/drivers/clk/ingenic/
H A Dcgu.c412 u32 div_reg, div; in ingenic_clk_recalc_rate() local
419 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
420 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()

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