Searched refs:div_m (Results 1 – 3 of 3) sorted by relevance
90 u8 div_m, div_n; in sun4i_ddc_set_rate() local93 ddc->m_offset, &div_m, &div_n); in sun4i_ddc_set_rate()96 SUN4I_HDMI_DDC_CLK_M(div_m) | in sun4i_ddc_set_rate()
192 u8 div_m; in tcon_ch1_set_rate() local195 tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half); in tcon_ch1_set_rate()200 reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK; in tcon_ch1_set_rate()
290 int div_m, div_n; in sunxi_nfc_set_clk_rate() local292 div_m = (clock_get_pll6() + hz - 1) / hz; in sunxi_nfc_set_clk_rate()293 for (div_n = 0; div_n < 3 && div_m > 16; div_n++) { in sunxi_nfc_set_clk_rate()294 if (div_m % 2) in sunxi_nfc_set_clk_rate()295 div_m++; in sunxi_nfc_set_clk_rate()296 div_m >>= 1; in sunxi_nfc_set_clk_rate()298 if (div_m > 16) in sunxi_nfc_set_clk_rate()299 div_m = 16; in sunxi_nfc_set_clk_rate()303 CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m), in sunxi_nfc_set_clk_rate()