Searched refs:div3 (Results 1 – 9 of 9) sorted by relevance
| /openbmc/linux/drivers/clk/uniphier/ |
| H A D | clk-uniphier.h | 118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
120 UNIPHIER_CLK_DIV2(parent, div2, div3)
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clock.h | 31 unsigned int div3; member
67 unsigned int div3; member
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | amlogic,a1-peripherals-clkc.yaml | 28 - description: input fixed pll div3
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| H A D | tesla,fsd-clock.yaml | 93 - description: PERIC shared0 div3 TBU clock (from CMU_CMU)
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 23 u32 div3; /* 20 */ member
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| /openbmc/linux/drivers/video/fbdev/aty/ |
| H A D | aty128fb.c | 1320 u32 div3; in aty128_set_pll() local
1339 div3 = aty_ld_pll(PPLL_DIV_3); in aty128_set_pll()
1340 div3 &= ~PPLL_FB3_DIV_MASK; in aty128_set_pll()
1341 div3 |= pll->feedback_divider; in aty128_set_pll()
1342 div3 &= ~PPLL_POST3_DIV_MASK; in aty128_set_pll()
1343 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1347 aty_st_pll(PPLL_DIV_3, div3); in aty128_set_pll()
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| /openbmc/linux/sound/soc/codecs/ |
| H A D | da7210.c | 216 u8 div3; member
1006 pll_div3 = da7210_pll_div[cnt].div3; in da7210_set_dai_pll()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | at91sam9n12.dtsi | 173 atmel,master-clk-have-div3-pres;
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| H A D | at91sam9x5.dtsi | 178 atmel,master-clk-have-div3-pres;
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