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Searched refs:div0 (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_zynq.c227 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
231 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_dci_rate()
235 zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1); in zynq_clk_get_dci_rate()
243 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
248 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynq_clk_get_peripheral_rate()
249 if (!div0) in zynq_clk_get_peripheral_rate()
250 div0 = 1; in zynq_clk_get_peripheral_rate()
265 zynq_clk_get_pll_rate(priv, pll), div0), in zynq_clk_get_peripheral_rate()
289 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs() argument
302 *div0 = d0; in zynq_clk_calc_peripheral_two_divs()
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H A Dclk_zynqmp.c419 u32 clk_ctrl, div0; in zynqmp_clk_get_peripheral_rate() local
430 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_peripheral_rate()
431 if (!div0) in zynqmp_clk_get_peripheral_rate()
432 div0 = 1; in zynqmp_clk_get_peripheral_rate()
447 DIV_ROUND_CLOSEST(pllrate, div0), div1); in zynqmp_clk_get_peripheral_rate()
454 u32 clk_ctrl, div0; in zynqmp_clk_get_wdt_rate() local
465 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT; in zynqmp_clk_get_wdt_rate()
466 if (!div0) in zynqmp_clk_get_wdt_rate()
467 div0 = 1; in zynqmp_clk_get_wdt_rate()
490 DIV_ROUND_CLOSEST(pllrate, div0), div1); in zynqmp_clk_get_wdt_rate()
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/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c141 div = readl(&clk->div0); in s5pc110_get_arm_clk()
161 div = readl(&clk->div0); in s5pc100_get_arm_clk()
182 div = readl(&clk->div0); in get_hclk()
199 div = readl(&clk->div0); in get_pclkd1()
225 div = readl(&clk->div0); in get_hclk_sys()
251 div = readl(&clk->div0); in get_pclk_sys()
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclock.h28 unsigned int div0; member
64 unsigned int div0; member
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h239 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) argument
/openbmc/u-boot/arch/arm/lib/
H A DMakefile7 lib1funcs.o uldivmod.o div0.o \
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_fp0_div.S9 div0.s \y0, \b
/openbmc/openbmc/poky/meta/recipes-devtools/clang/clang/
H A D0002-compiler-rt-support-a-new-embedded-linux-target.patch172 + div0 \
258 + cmpdf2 cmpsf2 div0 \
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc17686 { "div0.s", ICLASS_DIV0_S,
17689 { "div0.d", ICLASS_DIV0_D,