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Searched refs:display_v_end (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_dsi_encoder.c47 uint32_t display_v_start, display_v_end; in mdp4_dsi_encoder_mode_set() local
69display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dsi_hsync_s… in mdp4_dsi_encoder_mode_set()
80 mdp4_write(mdp4_kms, REG_MDP4_DSI_DISPLAY_VEND, display_v_end); in mdp4_dsi_encoder_mode_set()
H A Dmdp4_dtv_encoder.c46 uint32_t display_v_start, display_v_end; in mdp4_dtv_encoder_mode_set() local
72display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp4_dtv_encoder_mode_set()
83 mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end); in mdp4_dtv_encoder_mode_set()
H A Dmdp4_lcdc_encoder.c221 uint32_t display_v_start, display_v_end; in mdp4_lcdc_encoder_mode_set() local
247display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + lcdc_hsync_… in mdp4_lcdc_encoder_mode_set()
258 mdp4_write(mdp4_kms, REG_MDP4_LCDC_DISPLAY_VEND, display_v_end); in mdp4_lcdc_encoder_mode_set()
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_encoder.c40 uint32_t display_v_start, display_v_end; in mdp5_vid_encoder_mode_set() local
90display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_s… in mdp5_vid_encoder_mode_set()
99 display_v_end -= mode->hsync_start - mode->hdisplay; in mdp5_vid_encoder_mode_set()
113 mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end); in mdp5_vid_encoder_mode_set()
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_intf.c103 u32 display_v_start, display_v_end; in dpu_hw_intf_setup_timing_engine() local
129 display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + in dpu_hw_intf_setup_timing_engine()
177 display_v_end -= p->h_front_porch; in dpu_hw_intf_setup_timing_engine()
213 DPU_REG_WRITE(c, INTF_DISPLAY_V_END_F0, display_v_end); in dpu_hw_intf_setup_timing_engine()
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c907 u32 display_v_start, display_v_end; in dp_catalog_panel_tpg_enable() local
919 display_v_end = ((vsync_period - (drm_mode->vsync_start - in dp_catalog_panel_tpg_enable()
924 display_v_end -= (drm_mode->hsync_start - drm_mode->hdisplay); in dp_catalog_panel_tpg_enable()
948 dp_write_p0(catalog, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); in dp_catalog_panel_tpg_enable()