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Searched refs:di_clk (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qm-ldb.c68 unsigned long di_clk, in imx8qm_ldb_set_phy_cfg() argument
74 phy_cfg->differential_clk_rate = is_split ? di_clk / 2 : di_clk; in imx8qm_ldb_set_phy_cfg()
89 unsigned long di_clk = adj->clock * 1000; in imx8qm_ldb_bridge_atomic_check() local
100 imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); in imx8qm_ldb_bridge_atomic_check()
111 imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, in imx8qm_ldb_bridge_atomic_check()
136 unsigned long di_clk = adjusted_mode->clock * 1000; in imx8qm_ldb_bridge_mode_set() local
151 clk_set_rate(imx8qm_ldb->clk_bypass, di_clk); in imx8qm_ldb_bridge_mode_set()
152 clk_set_rate(imx8qm_ldb->clk_pixel, di_clk); in imx8qm_ldb_bridge_mode_set()
154 imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, false, phy_cfg); in imx8qm_ldb_bridge_mode_set()
162 imx8qm_ldb_set_phy_cfg(imx8qm_ldb, di_clk, is_split, true, in imx8qm_ldb_bridge_mode_set()
H A Dimx8qxp-ldb.c66 unsigned long di_clk, bool is_split, in imx8qxp_ldb_set_phy_cfg() argument
73 phy_cfg->differential_clk_rate = di_clk / 2; in imx8qxp_ldb_set_phy_cfg()
76 phy_cfg->differential_clk_rate = di_clk; in imx8qxp_ldb_set_phy_cfg()
94 unsigned long di_clk = adj->clock * 1000; in imx8qxp_ldb_bridge_atomic_check() local
105 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); in imx8qxp_ldb_bridge_atomic_check()
136 unsigned long di_clk = adjusted_mode->clock * 1000; in imx8qxp_ldb_bridge_mode_set() local
162 clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); in imx8qxp_ldb_bridge_mode_set()
163 clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); in imx8qxp_ldb_bridge_mode_set()
165 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); in imx8qxp_ldb_bridge_mode_set()
/openbmc/linux/drivers/gpu/drm/imx/ipuv3/
H A Dimx-tve.c121 struct clk *di_clk; member
263 clk_set_rate(tve->di_clk, rounded_rate / div); in imx_tve_encoder_mode_set()
265 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); in imx_tve_encoder_mode_set()
427 tve->di_clk = devm_clk_register(tve->dev, &tve->clk_hw_di); in tve_clk_init()
428 if (IS_ERR(tve->di_clk)) { in tve_clk_init()
430 PTR_ERR(tve->di_clk)); in tve_clk_init()
431 return PTR_ERR(tve->di_clk); in tve_clk_init()
H A Dimx-ldb.c167 unsigned long serial_clk, unsigned long di_clk) in imx_ldb_set_clock() argument
180 (long int)di_clk); in imx_ldb_set_clock()
181 clk_set_rate(ldb->clk[chno], di_clk); in imx_ldb_set_clock()
260 unsigned long di_clk = mode->clock * 1000; in imx_ldb_encoder_atomic_mode_set() local
285 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); in imx_ldb_encoder_atomic_mode_set()
286 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); in imx_ldb_encoder_atomic_mode_set()
290 di_clk); in imx_ldb_encoder_atomic_mode_set()
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1.c300 static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
962 &di_clk.common,
1114 [CLK_DI] = &di_clk.common.hw,