Searched refs:deferred_reg_writes (Results 1 – 4 of 4) sorted by relevance
491 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { in dpp3_deferred_update()493 dpp_base->deferred_reg_writes.bits.disable_dscl = false; in dpp3_deferred_update()496 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { in dpp3_deferred_update()502 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; in dpp3_deferred_update()505 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { in dpp3_deferred_update()511 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; in dpp3_deferred_update()514 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { in dpp3_deferred_update()520 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; in dpp3_deferred_update()523 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { in dpp3_deferred_update()529 dpp_base->deferred_reg_writes.bits.disable_shaper = false; in dpp3_deferred_update()[all …]
141 dpp_base->deferred_reg_writes.bits.disable_gamcor = true; in dpp3_power_on_gamcor_lut()
58 union defer_reg_writes deferred_reg_writes; member
170 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()