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Searched refs:ddrpllcfg0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/qemu/hw/misc/
H A Dsifive_u_prci.c37 return s->ddrpllcfg0; in sifive_u_prci_read()
78 s->ddrpllcfg0 = val32; in sifive_u_prci_write()
80 s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; in sifive_u_prci_write()
82 s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK; in sifive_u_prci_write()
140 s->ddrpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF | in sifive_u_prci_reset()
/openbmc/qemu/include/hw/misc/
H A Dsifive_u_prci.h75 uint32_t ddrpllcfg0; member