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Searched refs:ddrpll_ctrl (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti816x.c98 unsigned int ddrpll_ctrl; /* offset 0x440 */ member
243 ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); in ddr_pll_bypass_ti816x()
246 writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); in ddr_pll_bypass_ti816x()
253 ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
256 writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
259 ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
262 writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
289 while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) in ddr_pll_init_ti816x()