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Searched refs:ddrccr (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dscg.h266 u32 ddrccr; /* SCG DDR Clock Control Register */ member
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c333 reg = readl(&scg1_regs->ddrccr); in scg_ddr_get_rate()
917 writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr); in scg_a7_ddrclk_init()