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Searched refs:ddrc_cfg (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/imx/imx8m/
H A Dddr4_init.c14 void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in ddr4_cfg_umctl2() argument
19 reg32_write(ddrc_cfg->reg, ddrc_cfg->val); in ddr4_cfg_umctl2()
20 ddrc_cfg++; in ddr4_cfg_umctl2()
59 ddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); in ddr_init()
H A Dlpddr4_init.c16 void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num) in lpddr4_cfg_umctl2() argument
21 reg32_write(ddrc_cfg->reg, ddrc_cfg->val); in lpddr4_cfg_umctl2()
22 ddrc_cfg++; in lpddr4_cfg_umctl2()
67 lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num); in ddr_init()
H A Dhelper.c140 saved_timing->ddrc_cfg = cfg; in dram_config_save()
142 cfg->reg = timing_info->ddrc_cfg[i].reg; in dram_config_save()
143 cfg->val = timing_info->ddrc_cfg[i].val; in dram_config_save()
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c44 u32 ddrc_cfg, tmp; in ddr_cfg_init() local
52 ddrc_cfg = DDRC_CFG_TYPE_DDR3 | DDRC_CFG_IMBA | in ddr_cfg_init()
60 ddrc_cfg |= BIT(21); in ddr_cfg_init()
62 writel(ddrc_cfg, ddr_ctl_regs + DDRC_CFG); in ddr_cfg_init()
/openbmc/u-boot/board/freescale/imx8mq_evk/
H A Dlpddr4_timing_b0.c1178 .ddrc_cfg = lpddr4_ddrc_cfg,
H A Dlpddr4_timing.c1311 .ddrc_cfg = lpddr4_ddrc_cfg,
/openbmc/u-boot/arch/arm/include/asm/arch-imx8m/
H A Dddr.h685 struct dram_cfg_param *ddrc_cfg; member