Searched refs:ddr_in32 (Results 1 – 7 of 7) sorted by relevance
28 while (ddr_in32(ptr) & bits) { in set_wait_for_bits_clear()263 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()286 temp32 = ddr_in32(&ddr->debug[25]); in fsl_ddr_set_memctl_regs()295 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()395 temp32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()514 cs0_bnds = ddr_in32(&ddr->cs0_bnds); in fsl_ddr_set_memctl_regs()515 cs1_bnds = ddr_in32(&ddr->cs1_bnds); in fsl_ddr_set_memctl_regs()516 cs2_bnds = ddr_in32(&ddr->cs2_bnds); in fsl_ddr_set_memctl_regs()517 cs3_bnds = ddr_in32(&ddr->cs3_bnds); in fsl_ddr_set_memctl_regs()541 mtcr = ddr_in32(&ddr->mtcr); in fsl_ddr_set_memctl_regs()[all …]
55 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; in fsl_ddr_get_version()56 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; in fsl_ddr_get_version()184 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info()186 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()193 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()200 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()237 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); in print_ddr_info()242 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; in print_ddr_info()371 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()376 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()[all …]
186 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()192 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()195 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; in fsl_ddr_set_memctl_regs()222 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()231 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()242 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); in fsl_ddr_set_memctl_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()2661 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()2666 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()2679 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()2691 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()2699 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()
38 static inline u32 ddr_in32(void __iomem *addr) in ddr_in32() function63 ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI)); in fsl_mc_inject_data_hi_show()73 ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO)); in fsl_mc_inject_data_lo_show()83 ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT)); in fsl_mc_inject_ctrl_show()289 err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); in fsl_mc_check()302 syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC); in fsl_mc_check()313 ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS), in fsl_mc_check()314 ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS)); in fsl_mc_check()379 err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT); in fsl_mc_isr()447 cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 + in fsl_ddr_init_csrows()[all …]
21 #define ddr_in32(a) in_le32(a) macro27 #define ddr_in32(a) in_be32(a) macro
446 tmp = ddr_in32(&ddr->eor); in erratum_a008850_post()533 tmp = ddr_in32(&ddr->ddr_cdr1); in ddr_enable_0v9_volt()