Home
last modified time | relevance | path

Searched refs:ddr3_write_pup_reg (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c201 ddr3_write_pup_reg( in ddr3_pbs_tx()
641 ddr3_write_pup_reg( in ddr3_pbs_rx()
653 ddr3_write_pup_reg(PUP_PBS_RX + in ddr3_pbs_rx()
700 ddr3_write_pup_reg in ddr3_pbs_rx()
712 ddr3_write_pup_reg in ddr3_pbs_rx()
748 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_pbs_rx()
1046 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_rx_shift_dqs_to_first_fail()
1072 ddr3_write_pup_reg(PUP_DQS_RD, CS0, in ddr3_rx_shift_dqs_to_first_fail()
1113 ddr3_write_pup_reg(offs + in lock_pups()
1220 ddr3_write_pup_reg( in ddr3_pbs_per_bit()
[all …]
H A Dddr3_write_leveling.c357 ddr3_write_pup_reg in ddr3_wl_supplement()
388 ddr3_write_pup_reg in ddr3_wl_supplement()
551 ddr3_write_pup_reg(PUP_WL_MODE, in ddr3_write_leveling_hw_reg_dimm()
626 ddr3_write_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
1184 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, 0, 0); in ddr3_write_leveling_single_cs()
1224 ddr3_write_pup_reg(PUP_WL_MODE, cs, PUP_BC, phase, in ddr3_write_leveling_single_cs()
1323 ddr3_write_pup_reg(PUP_WL_MODE, cs, pup_num, phase, delay); in ddr3_write_leveling_single_cs()
H A Dddr3_dqs.c397 ddr3_write_pup_reg(adll_addr, cs, pup + in ddr3_find_adll_limits()
986 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_i_search()
1087 ddr3_write_pup_reg(PUP_DQS_RD, in ddr3_special_pattern_i_search()
1146 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_ii_search()
1238 ddr3_write_pup_reg(PUP_DQS_RD, in ddr3_special_pattern_ii_search()
1312 ddr3_write_pup_reg(PUP_DQS_WR, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()
1316 ddr3_write_pup_reg(PUP_DQS_RD, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()
H A Dddr3_read_leveling.c292 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
442 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
796 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
H A Dddr3_hw_training.h326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
H A Dddr3_sdram.c415 ddr3_write_pup_reg(pup_addr + in ddr3_sdram_pbs_compare()
H A Dddr3_hw_training.c547 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() function