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Searched refs:ddr3_set_sw_wl_rl_debug (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c36 extern void ddr3_set_sw_wl_rl_debug(u32);
279 ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL); in ddr3_init()
H A Dddr3_hw_training.c67 void ddr3_set_sw_wl_rl_debug(u32 val) in ddr3_set_sw_wl_rl_debug() function