Searched refs:ddr2xdqsclk (Results 1 – 2 of 2) sorted by relevance
221 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, in cm_basic_init()222 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()274 ret = cm_write_with_phase(cfg->ddr2xdqsclk, in cm_basic_init()275 &clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
40 u32 ddr2xdqsclk; member87 u32 ddr2xdqsclk; member