| /openbmc/linux/arch/powerpc/platforms/4xx/ |
| H A D | pci.c | 896 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
1023 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1323 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */ in ppc405ex_pciex_init_port_hw()
1332 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc405ex_pciex_init_utl()
1462 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, in ppc4xx_pciex_port_init_mapping()
1464 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, in ppc4xx_pciex_port_init_mapping()
1468 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1471 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, in ppc4xx_pciex_port_init_mapping()
1473 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, in ppc4xx_pciex_port_init_mapping()
1477 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
[all …]
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| H A D | cpm.c | 70 dcr_write(cpm.dcr_host, cpm.dcr_offset[cpm_reg], value | mask); in cpm_set()
103 dcr_write(cpm.dcr_host, cpm.dcr_offset[CPM_ER], er_save); in cpm_idle_sleep()
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | dcr.h | 32 #define dcr_write(host, dcr_n, value) dcr_write_generic(host, dcr_n, value) macro
42 #define dcr_write(host, dcr_n, value) dcr_write_native(host, dcr_n, value) macro
49 #define dcr_write(host, dcr_n, value) dcr_write_mmio(host, dcr_n, value) macro
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| /openbmc/qemu/hw/ppc/ |
| H A D | ppc.c | 1422 dcr_write_cb dcr_write; member
1464 if (dcr->dcr_write == NULL) in ppc_dcr_write()
1467 (*dcr->dcr_write)(dcr->opaque, dcrn, val); in ppc_dcr_write()
1479 dcr_read_cb dcr_read, dcr_write_cb dcr_write) in ppc_dcr_register() argument
1492 dcr->dcr_write != NULL) in ppc_dcr_register()
1496 dcr->dcr_write = dcr_write; in ppc_dcr_register()
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| H A D | ppc4xx_devs.c | 529 dcr_read_cb dcr_read, dcr_write_cb dcr_write) in ppc4xx_dcr_register() argument
532 ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); in ppc4xx_dcr_register()
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| /openbmc/qemu/include/hw/ppc/ |
| H A D | ppc4xx.h | 44 dcr_read_cb dcr_read, dcr_write_cb dcr_write);
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| H A D | ppc.h | 69 dcr_read_cb drc_read, dcr_write_cb dcr_write);
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| /openbmc/linux/drivers/net/ethernet/ibm/emac/ |
| H A D | mal.h | 220 dcr_write(mal->dcr_host, reg, val); in set_mal_dcrn()
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| /openbmc/linux/arch/powerpc/platforms/cell/ |
| H A D | axon_msi.c | 90 dcr_write(msic->dcr_host, dcr_n, val); in msic_dcr_write()
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| /openbmc/linux/drivers/video/fbdev/ |
| H A D | xilinxfb.c | 177 dcr_write(drvdata->dcr_host, offset, val); in xilinx_fb_out32()
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| /openbmc/linux/drivers/dma/ppc4xx/ |
| H A D | adma.c | 671 dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CF2H, byte_count); in ppc440spe_desc_set_rxor_block_size()
4332 dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_XORBA, val); in enable_store()
4393 dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL, reg); in poly_store()
4473 dcr_write(i2o_dcr_host, DCRN_I2O0_IBAH, (u32)(i2o_res.start >> 32)); in ppc440spe_configure_raid_devices()
4474 dcr_write(i2o_dcr_host, DCRN_I2O0_IBAL, (u32)(i2o_res.start) | in ppc440spe_configure_raid_devices()
4520 dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_BAUH, DMA_CUED_XOR_HB); in ppc440spe_configure_raid_devices()
4527 dcr_write(ppc440spe_mq_dcr_host, DCRN_MQ0_CFBHL, in ppc440spe_configure_raid_devices()
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| /openbmc/linux/drivers/net/ethernet/xilinx/ |
| H A D | ll_temac_main.c | 254 dcr_write(lp->sdma_dcrs, reg, value); in temac_dma_dcr_out()
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | mpic.c | 199 dcr_write(rb->dhost, reg, value); in _mpic_write()
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