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Searched refs:data_value (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training.c340 u32 data_value = 0, cs_cnt = 0, in hws_ddr3_tip_init_controller() local
392 data_value = (0x4000 | 0 | 0x1000000) & ~(1 << 26); in hws_ddr3_tip_init_controller()
394 data_value = (0x4000 | 0x8000 | 0x1000000) & ~(1 << 26); in hws_ddr3_tip_init_controller()
400 SDRAM_CFG_REG, data_value, in hws_ddr3_tip_init_controller()
460 data_value = 0x7; in hws_ddr3_tip_init_controller()
472 data_value = in hws_ddr3_tip_init_controller()
524 data_value = in hws_ddr3_tip_init_controller()
529 MR0_REG, data_value, in hws_ddr3_tip_init_controller()
551 data_value = (cwl_mask_table[cwl_val] << 3); in hws_ddr3_tip_init_controller()
552 data_value |= in hws_ddr3_tip_init_controller()
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H A Dddr3_training_ip_flow.h68 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
78 u32 reg_addr, u32 data_value, u32 reg_mask);
85 u32 data_value);
H A Dddr3_debug.c113 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
145 &data_value)); in ddr3_tip_reg_dump()
146 printf("0x%x ", data_value); in ddr3_tip_reg_dump()
156 &data_value)); in ddr3_tip_reg_dump()
157 printf("0x%x ", data_value); in ddr3_tip_reg_dump()
675 u32 data_value; in ddr3_tip_read_adll_value() local
693 &data_value)); in ddr3_tip_read_adll_value()
696 data_value & mask; in ddr3_tip_read_adll_value()
744 u32 data_value; in read_phase_value() local
758 &data_value)); in read_phase_value()
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H A Dddr3_training_pbs.c942 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; in ddr3_tip_print_pbs_result() local
975 &data_value)); in ddr3_tip_print_pbs_result()
976 printf("%d , ", data_value); in ddr3_tip_print_pbs_result()
H A Dddr3_training_ip_engine.c631 u32 data_value = 0; in ddr3_tip_configure_odpg() local
634 data_value = ((single_pattern << 2) | (tx_phases << 5) | in ddr3_tip_configure_odpg()
639 ODPG_DATA_CTRL_REG, data_value, 0xaffffffc); in ddr3_tip_configure_odpg()
/openbmc/qemu/hw/gpio/
H A Daspeed_gpio.c268 uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); in aspeed_evaluate_irq()
307 uint32_t old = regs->data_value; in aspeed_gpio_update()
330 regs->data_value |= mask; in aspeed_gpio_update()
332 regs->data_value &= ~mask; in aspeed_gpio_update()
358 reg_val = s->sets[set_idx].data_value; in aspeed_gpio_get_pin_level()
366 uint32_t value = s->sets[set_idx].data_value; in aspeed_gpio_set_pin_level()
611 value = set->data_value; in aspeed_gpio_read()
692 reg_value = update_value_control_source(set, set->data_value, in aspeed_gpio_write_index_mode()
802 aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); in aspeed_gpio_write_index_mode()
851 data = update_value_control_source(set, set->data_value, data); in aspeed_gpio_write()
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/openbmc/qemu/include/hw/gpio/
H A Daspeed_gpio.h96 uint32_t data_value; /* Reflects pin values */ member