Searched refs:d3cfgr (Results 1 – 1 of 1) sorted by relevance
128 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */ member635 u32 d1cfgr, d3cfgr; in stm32_clk_get_rate() local712 d3cfgr = readl(®s->d3cfgr); in stm32_clk_get_rate()713 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { in stm32_clk_get_rate()715 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> in stm32_clk_get_rate()