Searched refs:d1cfgr (Results 1 – 1 of 1) sorted by relevance
126 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */ member413 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK, in configure_clocks()635 u32 d1cfgr, d3cfgr; in stm32_clk_get_rate() local669 d1cfgr = readl(®s->d1cfgr); in stm32_clk_get_rate()671 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) { in stm32_clk_get_rate()673 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >> in stm32_clk_get_rate()678 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) { in stm32_clk_get_rate()680 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER; in stm32_clk_get_rate()698 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) { in stm32_clk_get_rate()700 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >> in stm32_clk_get_rate()